Table of Contents

• Radiation- and Temperature-Induced Fault Modeling and Simulation in BiCMOS LSI's Components using RAD-THERM TCAD SubsystemKonstantin O. Petrosyants, Maxim Kozhukhov, Dmitry Popov. 1-4 [doi]
• Modular Data Link Layer Processing for THz communicationLukasz Lopacinski, Mohamed Hussein Eissa, Goran Panic, Alireza Hasani, R. Kraemer. 1-5 [doi]
• Hardware and control design of a ball balancing robotIoana Lal, Marius Nicoara, Alexandru Codrean, Lucian Busoniu. 1-6 [doi]
• A 5 to 10.5 GHz Low-power Wideband I/Q Transmitter with Integrated Current-Mode Logic Frequency DividerHwann-Kaeo Chiou, Wei-Min Sung. 1-4 [doi]
• A Sketch Classifier Technique with Deep Learning Models Realized in an Embedded SystemTsung-Han Tsai, Po-Ting Chi, Kuo-Hsing Cheng. 1-4 [doi]
• Fault Tolerant Control System of the Rotary Hearth Furnace Servicing MachinesVlad Muresan, Mihail Abrudean. 1-6 [doi]
• A new FPGA-based Detection Method for Spurious Variations in PCBA Power Distribution NetworkSergei Odintsov, Ludovica Bozzoli, Corrado De Sio, Luca Sterpone, Artur Jutman. 1-6 [doi]
• FPGA-based SIFT implementation for wearable computingAttila Fejer, Zoltán Nagy, Jenny Benois-Pineau, Péter Szolgay, Aymar de Rugy, Jean-Philippe Domenger. 1-4 [doi]
• Analyzing and Optimizing the Dummy Rounds SchemeStanislav Jerabek, Jan Schmidt. 1-4 [doi]
• Using Voters May Lead to Secret LeakageJan Belohoubek, Petr Fiser, Jan Schmidt. 1-4 [doi]
• Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital SystemsChing-Hwa Cheng, Tang-Chieh Liu. 1-4 [doi]
• Acceleration of Feature Extraction for Real-Time Analysis of Encrypted Network TrafficRoman Vrana, Jan Korenek, David Novak. 1-6 [doi]
• Nonlinear Compression Codes Used In IC TestingOndrej Novák. 1-4 [doi]
• Fault-Aware Performance Assessment Approach for Embedded NetworksJan Malburg, Karl Janson, Jaan Raik, Frank Dannemann. 1-4 [doi]
• Design of a True Random Number Generator Based on Low Power Oscillator with Increased JitterMariusz Derlecki, Krzysztof Siwiec, Pawel Narczyk, Witold A. Pleskacz. 1-4 [doi]
• From Constraints to Tape-Out: Towards a Continuous AMS Design FlowAndreas Krinke, Tilman Horst, Georg Gläser, Martin Grabmann, Tobias Markus, Benjamin Prautsch, Uwe Hatnik, Jens Lienig. 1-10 [doi]
• Architecture-aware Memory Access Scheduling for High-throughput Cascaded ClassifiersHsiang-Chih Hsiao, Chun-Wei Chen, Jonas Wang, Ming-Der Shieh, Pei-Yin Chen. 1-4 [doi]
• Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430Karel Szurman, Zdenek Kotásek. 1-4 [doi]
• Encryption-Based Secure JTAGEmanuele Valea, Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre. 1-6 [doi]
• Hybrid on-line self-test architecture for computational units on embedded processor coresAndrea Floridia, Gianmarco Mongano, Davide Piumatti, Ernesto Sánchez 0001. 1-6 [doi]
• New categories of Safe Faults in a processor-based Embedded SystemCemil Cem Gürsoy, Maksim Jenihhin, Adeboye Stephen Oyeniran, Davide Piumatti, Jaan Raik, Matteo Sonza Reorda, Raimund Ubar. 1-4 [doi]
• Effective Screening of Automotive SoCs by Combining Burn-In and System Level TestF. Almeida, Paolo Bernardi, D. Calabrese, Marco Restifo, Matteo Sonza Reorda, Davide Appello, Giorgio Pollaccia, Vincenzo Tancorre, R. Ugioli, G. Zoppi. 1-6 [doi]
• Implementation of FPGA-based Accelerator for Deep Neural NetworksTsung-Han Tsai, Yuan-Chen Ho, Ming-Hwa Sheu. 1-4 [doi]
• On the in-field test of the GPGPU scheduler memoryStefano Di Carlo, Josie E. Rodriguez Condia, Matteo Sonza Reorda. 1-6 [doi]
• Investigation of Low-Voltage, Sub-threshold Charge Pump with Parasitics Aware Design MethodologyMartin Kovác, Daniel Arbet, Viera Stopjaková, Michal Sovcik, Lukás Nagy. 1-4 [doi]
• Hardware Trojan Detection and Recovery in MPSoCs via On-line Application Specific TestingAmin Malekpour, Roshan G. Ragel, Daniel Murphy, Aleksandar Ignjatovic, Sri Parameswaran. 1-6 [doi]
• High side power MOSFET switch driver for a low-power AC/DC converterMiroslav Potocný, Juraj Brenkus, Viera Stopjaková. 1-6 [doi]
• Automated Integration of Dynamic Power Management into FPGA-Based DesignMichal Skuta, Dominik Macko. 1-4 [doi]
• Hash-based Pattern Matching for High Speed NetworksTomas Fukac, Jan Korenek. 1-5 [doi]
• Testability Measures Considering Circuit Reconvergence to Reduce ATPG RuntimeKai-Hsun Chen, Ching-Yuan Chen, Jiun-Lang Huang. 1-2 [doi]
• Efficient Error Recovery Scheme in Fault-tolerant NoC ArchitecturesMartin Strava. 1-4 [doi]
• Development of wearable hardware platform to measure the ECG and EMG with IMU to detect motion artifactsMuhammad Tanweer, Kari A. I. Halonen. 1-4 [doi]
• Generic Error Localization for the Electronic System LevelSebastian Pointner, Pablo González de Aledo, Robert Wille. 1-4 [doi]
• Ultra Low-Voltage Rail-to-Rail Comparator Design in 130 nm CMOS TechnologyLukás Nagy, Daniel Arbet, Martin Kovác, Miroslav Potocný, Viera Stopjaková. 1-6 [doi]
• Low Latency Hardware-Accelerated Dynamic Memory Manager for Hard Real-Time and Mixed-Criticality SystemsLukas Kohutka, Lukás Nagy, Viera Stopjaková. 1-6 [doi]