Jakub Podivinsky, Marcela imkova, Ondrej Cekan, Zdenek Kotásek. FPGA Prototyping and Accelerated Verification of ASIPs. In Zoran Stamenkovic, Witold A. Pleskacz, Jaan Raik, Heinrich Theodor Vierhaus, editors, 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2015, Belgrade, Serbia, April 22-24, 2015. pages 145-148, IEEE, 2015. [doi]
Abstract is missing.