Table of Contents

• Fast worst-case peak temperature evaluation for real-time applications on multi-core systemsLars Schor, Iuliana Bacivarov, Hoeseok Yang, Lothar Thiele. 1-6 [doi]
• Detailed analysis of compilation options for robust software-based embedded systemsA. Wecxsteen, Salma Bergaoui, Régis Leveugle. 1-6 [doi]
• Low voltage testing for interconnect opens under process variationsJesus Moreno, Víctor H. Champac, Michel Renovell. 1-6 [doi]
• Fast and scalable temperature-driven floorplan design in 3D MPSoCsIgnacio Arnaldo, Alessandro Vincenzi, José Luis Ayala, José Luis Risco-Martín, José Ignacio Hidalgo, Martino Ruggiero, David Atienza. 1-6 [doi]
• Simulation of SET faults in a voltage controlled oscillatorWalter E. Calienes Bartra, Fernanda Lima Kastensmidt, Ricardo Reis. 1-6 [doi]
• Automatic generation of an FPGA based embedded test system for printed circuit board testingJorge H. Meza Escobar, J. SachBe, Steffen Ostendorff, Heinz-Dietrich Wuttke. 1-6 [doi]
• Design-for-manufacturability of MEMS convective accelerometers through adaptive electrical calibration strategyAhmed Amine Rekik, Florence Azaïs, Frédérick Mailly, Pascal Nouet. 1-6 [doi]
• Self-optimization of dense wireless sensor networks based on simulated annealingAlex R. Pinto, Adriano Mauro Cansian, José Marcio Machado, Carlos Montez. 1-6 [doi]
• Selective hardening methodology for combinational logicSamuel Nascimento Pagliarini, Lirida A. B. Naviner, Jean-François Naviner. 1-6 [doi]
• Pattern-based injections in processors implemented on SRAM-based FPGAsMohamed Ben Jrad, Régis Leveugle. 1-4 [doi]
• Non-intrusive fault tolerance in soft processors through circuit duplicationFrederico Ferlini, Felipe A. da Silva, Eduardo Augusto Bezerra, Djones Vinicius Lettnin. 1-6 [doi]
• Simulation framework for multilevel power estimation and timing analysis of digital systems allowing the consideration of thermal effectsGergely Nagy, András Poppe. 1-5 [doi]
• Impact of TID-induced threshold deviations in analog building-blocks of operational amplifiersGuilherme S. Cardoso, Tiago R. Balen, Marcelo Soares Lubaszewski, Rafael Galhardo Vaz, Odair Lelis Goncalez. 1-6 [doi]
• Diagnosis and correction of multiple design errors using critical path tracing and mutation analysisHanno Hantson, Urmas Repinski, Jaan Raik, Maksim Jenihhin, Raimund Ubar. 1-6 [doi]
• Parametric DC and noise measurements in a unified test & characterization software tool frameworkJose A. Rodriguez, Manuel Jimenez, William Morales, Fan-Chi Hou, Lucianne Millan, Rogelio Palomera. 1-6 [doi]
• About robustness of test patterns regarding multiple faultsRaimund Ubar, Sergei Kostin, Jaan Raik. 1-6 [doi]
• Retiming scan circuit to eliminate timing penaltyOzgur Sinanoglu, Vishwani D. Agrawal. 1-6 [doi]
• Acquiring real-time heating of cells in standard cell designsAndrás Timár, Márta Rencz. 1-5 [doi]
• Built-in self-diagnosis targeting arbitrary defects with partial pseudo-exhaustive testAlejandro Cook, Sybille Hellebrand, Michael E. Imhof, Abdullah Mumtaz, Hans-Joachim Wunderlich. 1-4 [doi]
• Variation-aware and self-healing design methodology for a system-on-chipJangjoon Lee, Srikar Bhagavatula, Kaushik Roy, Byunghoo Jung. 1-4 [doi]
• Model-based design for wireless body sensor network nodesIvan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza, Donatella Sciuto. 1-6 [doi]
• SET susceptibility estimation of clock tree networks from layout extractionRaul Chipana, Fernanda Lima Kastensmidt, Jorge Tonfat, Ricardo Reis. 1-6 [doi]
• PSL assertion checkers synthesis with ASM based HLS tool ABELITEMaksim Jenihhin, Samary Baranov, Jaan Raik, Valentin Tihhomirov. 1-6 [doi]
• Configurable tool to protect processors against SEE by software-based detection techniquesEduardo Chielle, Raul Sergio Barth, Angelo Cardoso Lapolli, Fernanda Lima Kastensmidt. 1-6 [doi]
• Applying adaptive temporal filtering for SET mitigation based on the propagation-delay of every logical pathJose Eduardo Pereira Souza, Fernanda Lima Kastensmidt. 1-6 [doi]
• Investigation of a CMOS oscillator concept for particle detection and diagnosisK. Castellani-Coulié, Hassen Aziza, Wenceslas Rahajandraibe, Gilles Micolau, Jean Michel Portal. 1-5 [doi]
• Built-in tuning of RFIC Passive Polyphase Filter by process and thermal monitoringFayrouz Haddad, Wenceslas Rahajandraibe, Hassen Aziza, K. Castellani-Coulié, Jean Michel Portal. 1-5 [doi]
• MoDiVHA: A hierarchical strategy for distributed test assignmentJefferson Paulo Koppe, Elias Procópio Duarte Jr., Luis C. E. Bona. 1-6 [doi]
• Mutation operators for concurrent programs in MPIRodolfo Adamshuk Silva, Simone do Rocio Senger de Souza, Paulo Sergio Lopes de Souza. 1-6 [doi]
• Investigating the use of an on-chip sensor to monitor NBTI effect in SRAMArthur Ceratti, Thiago Copetti, Letícia Maria Veiras Bolzani, F. Vargas. 1-6 [doi]
• SITARe: A simulation tool for analysis and diagnosis of radiation effectsGilles Micolau, K. Castellani-Coulié, Hassen Aziza, Jean Michel Portal. 1-5 [doi]
• Multi-condition alternate test of analog, mixed-signal, and RF systemsManuel J. Barragan Asian, Gildas Leger, José Luis Huertas. 1-6 [doi]
• SEU fault-injection in VHDL-based processors: A case studyWassim Mansour, Raoul Velazco. 1-5 [doi]
• A guiding heuristic for the semi-formal verification of high-level designsAlair Dias Junior, Diogenes C. da Silva Junior. 1-6 [doi]
• Platform for automated HW/SW co-verification, testing and simulation of microprocessorsAleksandar Simevski, Rolf Kraemer, Milos Krstic. 1-5 [doi]
• Low-power design under variation using error prevention and error tolerance (invited paper)Kwanyeob Chae, Minki Cho, Saibal Mukhopadhyay. 1-6 [doi]
• Implementing a Self-Checking PROFIBUS SlaveMargrit Reni Krug, Marcelo Lubaszewski, José Manuel Martins Ferreira, Gustavo Ribeiro da Costa Alves. 4-8
• Self Test Built-in Plan for Data-Path Functional UnitsJose Artur Quilici González, José Roberto de A. Amazonas, Marius Strum, Wang Jiang Chau. 9-14
• A Self-Testing Mask Programmable Matrix Using Built-in Current SensingFernanda Gusmão de Lima, Eduardo D'Avila, Mauricio Moraes, Marcelo Lubaszewski, Ricardo Reis 0001. 15-19
• FTRT_OS - A Fault-Tolerant Operating System for Real-Time Applications: An Experience with Digital Signal Processor (DSP) ArchitectureHelano S. Castro, Regis C. de Araujo, Giovanni C. Barroso. 22-28
• Fault-Tolerance in VHDL Description: Transient-Fault Injection & Early Reliability EstimationFabian Vargas 0001, Alexandre M. Amory, Raoul Velazco. 29-35
• Hardening the Software with Respect to Transient Errors: a Method and Experimental ResultsPh. Cheynet, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante. 36-40
• Defect Oriented Testing of an ECL/CMOS Level Converter CircuitMin-Hsing P. Chen, André Ivanov, Sassan Tabatabaei. 42-46
• Detectability Dependency on Test Generation Process for Interconnection OpensAntonio Zenteno, Víctor H. Champac, Joan Figueras. 47-53
• Transient Current Monitoring Using a Current-to-Frequency ConverterRodrigo Picos, J. Colom, Miquel Roca, Eugeni Isern, Jaume Segura 0001, Oscar Calvo, Eugenio García Moreno. 54-58
• Charge Sharing Fault Analysis and Testing for CMOS Domino Logic CircuitsChing-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone. 59-64
• Experiments on RTL ATPG and Fault Simulation for High Defect Coverage in Digital Systems-on-a-ChipMarcelino B. Santos, João Paulo Teixeira 0001. 66-71
• A Quick and Inexpensive Method to Identify False Critical Paths Using ATPG Techniques: an Experiment with a PowerPC MicroprocessorJayanta Batra, Magdy S. Abadir, Jacob A. Abraham. 72-76
• Testability of Circuits Derived from Lattice DiagramsRolf Drechsler, Wolfgang Günther 0001, Bernd Becker 0001. 77-81
• Mixed-Signal Test Bus IEEE 1149.4 Compatible BIST Scheme for Classical 2nd Order Filter Approximations using the Transient Response Analysis MethodJosé Vicente Calvano, Vladimir Castro Alves, Marcelo Soares Lubaszewski. 84-87
• On the Temperature Dependencies of Analog BISTLuigi Carro, Michel Renovell, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs. 88-93
• Deterministic Built-In Self -Test for Shifters, Adders and ALUs in DatapathsMihalis Psarakis, Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. 98-103
• On the Study of a New BIST Technique Using Reseeding of Linear Feedback Shift Register toAccelerate the TestS. Caceres, J. M. Ruiz, F. A. Trelles, J. A. Domingues, S. de Pablo. 104-109
• Cost/Quality Trade-Off in Synthesis for BISTPeter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki. 110-115
• Minimizing the Hardware Overhead of a Histogram-Based BIST Scheme for Analog-to-Digital ConvertersSerge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell. 118-122
• Alternative DFT Strategies for High-Speed Pipelined Data ConvertersEduardo J. Peralías, Adoración Rueda, José L. Huertas. 123-127
• Block-Based Test Integration for Analog Integrated CircuitsSule Ozev, Alex Orailoglu. 128-132
• Synthesis of a 8051-Like Microcontroller Tolerant to Transient FaultsÉrika F. Cota, Marcelo Lubaszewski, Raoul Velasco, Sana Rezgui. 134-139
• Fail-Safe and Test for Electronic Control Systems Using PLCsJorge Marcos, Ana Gomez, Enrique Mandado, Carlos Peñalver, Alfonso Lago. 140-145
• Merging BIST and Configurable Computing Technology to Improve Availability in Space ApplicationsEduardo Bezerra 0001, Fabian Vargas 0001, Michael Paul Gough. 146-151
• A Synchronous Testing Strategy for Hierarchical Adaptive Distributed System-Level DiagnosisAlessandro Brawerman, Elias P. Duarte Jr.. 154-161
• Reliable Diagnosis of Grid-Connected SystemsAntonio Caruso 0001, Stefano Chessa, Piero Maestrini, Paolo Santi. 162-165
• A Token-Based Testing Strategy for Non-Broadcast Network DiagnosisJadson Igor Siqueira, Eduardo Fabris, Elias P. Duarte Jr.. 166-171
• Electronic Process Limited YieldGary W. Maier, Shawn Smith. 174-180
• Determination of Silicon Film Thickness in SOI CapacitorsVictor Sonnenberg, João Antonio Martino. 181-184
• The Use of Macromodels on Op-Amp Circuits Fault ModelingJosé Vicente Calvano, Vladimir Castro Alves, Marcelo Lubaszewski. 188-192
• On-Line BIST for Testing Analog CircuitsJaime Velasco-Medina, Iyad Rayane, Michael Nicolaidis. 193-195
• RSM and Simplex Optimization for Parametric Fault Diagnosis of Analog Integrated CircuitsGuillermo Espinosa Flores-Verdad, José Luis Vázquez-González. 196-200
• Test Configuration Generation for FPGA Logic CellsMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 202-208
• Using Reconfigurability Features to Break Down Test Costs: a Case StudyLuigi Carro, Luciano Agostini, Roberto Pacheco, Marcelo Lubaszewski. 209-214
• The Test-Cycle Minimization in Parameterized Bus-Oriented Datapath DesignsV. A. Zivkovic, Ronald J. W. T. Tangelder, H. G. Herkhoff. 215-220
• Path Selection Strategies in the Context of Software Testing CriteriaLeticia Mara Peres, Silvia Regina Vergilio, Mario Jino, José Carlos Maldonado. 222-227
• Constraint Based Criteria: An Approach for Test Case Selection in the Structural TestingSilvia Regina Vergilio, José Carlos Maldonado, Mario Jino. 228-234
• Codesign System Modeling for Performance AnalysisLuiza de Macedo Mourelle, Nadia Nedjah. 235-242
• Design Optimization Based on Diagnosis TechniquesAndreas G. Veneris, Magdy S. Abadir, Ibrahim N. Haji. 244-249
• Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line TestYorgos Makris, Alex Orailoglu. 250-255
• Formal Approach to the RTL Testability AnalysisZdenek Kotásek, Richard Ruzicka, Jan Hlavicka. 256-261
• A New Method to Extract the Silicon Film Thickness of Enhancement Mode Fully Depleted SOIN MOSFETsA. S. Nicolett, João A. Martino, E. Simoen, C. Claeys, Marcelo Bellodi, M. A. Pavanello, A. S. Nicolett. 264-267