Table of Contents

• On-line test of embedded systems: Which role for functional test?Matteo Sonza Reorda. 1 [doi]
• TSV based 3D stacked ICs: Opportunities and challengesSaid Hamdioui. 2 [doi]
• Vertical Slit Transistor based Integrated Circuits (VeSTICs)Andrzej Pfitzner. 3 [doi]
• 3D integration: Opportunities, design challenges and approachesUwe Knöchel. 4 [doi]
• Asynchronous circuit design: From basics to practical applicationsEckhard Grass, Milos Krstic, Xin Fan, Steffen Zeidler. 5 [doi]
• Automated synthesis and design-error repair of systemsGeorg Hofferek. 6 [doi]
• Fault management in an IEEE P1687 (IJTAG) environmentErik Larsson, Konstantin Sibin. 7 [doi]
• Design methodology for fault tolerant ASICsVladimir Petrovic, Marko Ilic, Günter Schoof, Zoran Stamenkovic. 8-11 [doi]
• Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdownHagen Sämrow, Claas Cornelius, Philipp Gorski, Andreas Tockhorn, Dirk Timmermann. 12-15 [doi]
• Synthesis of Petri nets into FPGA with operation flexible memoriesArkadiusz Bukowiec, Marian Adamski. 16-21 [doi]
• An evaluation of the application dependent FPGA test methodMartin Rozkovec, Jiri Jenícek, Ondrej Novák. 22-25 [doi]
• AGATE - towards designing a low-power chip multithreading processor for mobile software defined radio systemsKrzysztof Marcinek, Witold A. Pleskacz. 26-29 [doi]
• Improving the iterative power of resynthesisPetr Fiser, Jan Schmidt. 30-33 [doi]
• NAND/NOR gate polymorphism in low temperature environmentRichard Ruzicka, Vaclav Simek. 34-37 [doi]
• Current sensing completion detection in dual-rail asynchronous systemsLukás Nagy, Viera Stopjaková. 38-41 [doi]
• Power constraint testing for multi-clock domain SoCs using concurrent hybrid BISTM. H. Haghbayan, Saeed Safari, Zainalabedin Navabi. 42-45 [doi]
• A low-overhead monitoring ring interconnect for MPSoC parameter optimizationAbdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf. 46-49 [doi]
• Design techniques for increasing performance and resource utilization of reconfigurable soft CPUsAlexander Wold, Dirk Koch, Jim Tørresen. 50-55 [doi]
• An automated infrastructure for real-time monitoring of multi-core Systems-on-ChipGeorge Kornaros, Ioannis Christoforakis, Maria Astrinaki. 56-61 [doi]
• The architecture and the technology characterization of an FPGA-based customizable Application-Specific Vector ProcessorJaroslav Sykora, Lukas Kohout, Roman Bartosinski, Leos Kafka, Martin Danek, Petr Honzík. 62-67 [doi]
• LC-VCO design automation tool for nanometer CMOS technologyKrzysztof Siwiec, Tomasz Borejko, Witold A. Pleskacz. 68-73 [doi]
• A gigabit fully integrated plastic optical fiber receiver for a RC-LED sourceAtef Mohamed, Robert Swoboda, Horst Zimmermann. 74-78 [doi]
• A low phase noise Ka-band voltage controlled oscillator using 0.15 µm GaAs pHEMT technologyHsuan-Ling Kao, S. P. Shih, Chih-Sheng Yeh, Li-Chun Chang. 79-82 [doi]
• A simulation framework for 3-dimension Networks-on-chip with different vertical channel density configurationsHaoyuan Ying, Ashok Jaiswal, Mohamed A. Abd El ghany, Thomas Hollstein, Klaus Hofmann. 83-88 [doi]
• HLS-DoNoC: High-level simulator for dynamically organizational NoCsLiang Guang, Ethiopia Nigussie, Juha Plosila, Jouni Isoaho, Hannu Tenhunen. 89-94 [doi]
• Low-area boundary BIST architecture for mesh-like network-on-chipJaan Raik, Vineeth Govind. 95-100 [doi]
• Test and configuration architecture of a sub-THz CMOS detector arrayPéter Földesy, Domonkos Gergelyi, Csaba Fuzy, Gergely Károlyi. 101-104 [doi]
• Automatic integration of hardware descriptions into system-level modelsRalph Görgen, Jan-Hendrik Oetjens, Wolfgang Nebel. 105-110 [doi]
• Multisine signal generation method for a bioimpedance measurement deviceMaksim Gorev, Vadim Pesonen, Peeter Ellervee. 111-114 [doi]
• Radiation-tolerant combinational gates - an implementation based comparisonVaradan Savulimedu Veeravalli, Andreas Steininger. 115-120 [doi]
• Monitoring-driven HW/SW interrupt overload prevention for embedded real-time systemsJosef Strnadel. 121-126 [doi]
• Efficient link-level error resilience in 3D NoCsVladimir Pasca, Saif-Ur Rehman, Lorena Anghel, Mounir Benabdenbi. 127-132 [doi]
• The design of dependable flexible multi-sensory System-on-Chips for security applicationsHans G. Kerkhoff, Yong Zhao. 133-138 [doi]
• System side-channel leakage emulation for HW/SW security coverification of MPSoCsArmin Krieg, Johannes Grinschgl, Christian Steger, Reinhold Weiss, Holger Bock, Josef Haid. 139-144 [doi]
• Security properties of oscillator rings in true random number generatorsKnut Wold, Slobodan Petrovic. 145-150 [doi]
• Differential evolutionary optimization algorithm applied to ESD MOSFET model fitting problemTomas Napravnik, Vlastimil Kote, Vladimir Molata, Jiri Jakovenko. 155-158 [doi]
• A three-dimensional DRAM using floating body cell in FDSOI devicesXuelian Liu, Aamir Zia, Mitchell R. LeRoy, Srikumar Raman, Ryan Clarke, Russell P. Kraft, John F. McDonald. 159-162 [doi]
• CDMA technique for Network-on-ChipAhmed A. El Badry, Mohamed A. Abd El ghany. 163-166 [doi]
• Application of IDDT test towards increasing SRAM reliability in nanometer technologiesGábor Gyepes, Daniel Arbet, Juraj Brenkus, Viera Stopjaková. 167-170 [doi]
• Evaluation of susceptibility of FPGA-based circuits to fault injection attacks based on clock glitchingJakub Korczyc, Andrzej Krasniewski. 171-174 [doi]
• D&T Presenter - electronic interactive system for design and test educationMatej Hlatký, Valter Martinek, Elena Gramatová. 175-178 [doi]
• A 1V, low power, high-gain, 3 - 11 GHz double-balanced CMOS sub-harmonic mixerRouhollah Feghhi, Sasan Naseh. 179-182 [doi]
• Reduction of complex safety models based on Markov chainsMartin Kohlík, Hana Kubátová. 183-186 [doi]
• Generation of SystemC/TLM code from UML/MARTE sequence diagrams for verificationEmad Samuel Malki Ebeid, Davide Quaglia, Franco Fummi. 187-190 [doi]
• A 512 kb SRAM in 65nm CMOS with divided bitline and novel two-stage sensing techniqueXiang Zheng, Ming Liu, Hong Chen, Huamin Cao, Cong Wang, Zhiqiang Gao. 191-192 [doi]
• OBIST strategy versus parametric test - Efficiency in covering catastrophic faults in active analog filtersDaniel Arbet, Gábor Gyepes, Juraj Brenkus, Viera Stopjaková. 193-194 [doi]
• Optimised Power Supply Unit DesignMartin Pospisilik, Milan Adamek. 195-196 [doi]
• Lightweight cipher resistivity against brute-force attack: Analysis of PRESENTJan Pospísil, Martin Novotný. 197-198 [doi]
• VHDLVisualizer: HDL model visualization with simulation-based verificationDominik Macko, Katarina Jelemenska. 199-200 [doi]
• Temperature and on-chip crosstalk measurement using ring oscillators in FPGAMartin Gag, Tim Wegner, Ansgar Waschki, Dirk Timmermann. 201-204 [doi]
• Adaptive voltage scaling by in-situ delay monitoring for an image processing circuitMartin Wirnshofer, Leonhard Heiß, Anil Narayan Kakade, Nasim Pour Aryan, Georg Georgakos, Doris Schmitt-Landsiedel. 205-208 [doi]
• Effective RT-level software-based self-testing of embedded processor coresParisa Kabiri, Zainalabedin Navabi. 209-212 [doi]
• High speed FPGA implementation of hough transform for real-time applicationsLiberis Voudouris, Spiridon Nikolaidis, Abdoul Rjoub. 213-218 [doi]
• Generation of non-overlapping clock signals without using a feedback loopRonald Spilka, Gerald Hilber, Andreas Rauchenecker, Dominik Gruber, Michael Sams, Timm Ostermann. 219-223 [doi]
• Design and implementation of high-performance high-valency ling addersTaskin Kocak, Preeti Patil. 224-229 [doi]
• A new SAT-based ATPG for generating highly compacted test setsStephan Eggersglüß, Rene Krenz-Baath, Andreas Glowatz, Friedrich Hapke, Rolf Drechsler. 230-235 [doi]
• Multiple stuck-at-fault detection theoremRaimund Ubar, Sergei Kostin, Jaan Raik. 236-241 [doi]
• Genetic method for compressed skewed-load delay test generationRoland Dobai, Marcel Baláz. 242-247 [doi]
• Auto-calibration techniques in built-in jitter measurement circuitChih-Ping Cheng, Jen-Chieh Liu, Kuo-Hsing Cheng. 248-249 [doi]
• Low power balun Design for 1.575 GHz in 90 nm CMOS rechnologyJacek Gradzki. 250-253 [doi]
• Digital-driven formal analog verification for asynchronously feed-backed circuitriesGürkan Uygur, Sebastian Sattler. 254-257 [doi]
• Bounded model checking of Contiki applicationsThilo Vörtler, Steffen Rülke, Petra Hofstedt. 258-261 [doi]
• Low power scan by partitioning and scan holdEfi Arvaniti, Yiorgos Tsiatouhas. 262-265 [doi]
• A user-level library for fault tolerance on shared memory multicore systemsHamid Mushtaq, Zaid Al-Ars, Koen Bertels. 266-269 [doi]
• A low voltage sigma delta modulator for temperature sensorYi-Hsiang Juan, Ching-Hsing Luo, Hong-Yi Huang. 270-273 [doi]
• Developing a new phase noise estimation technique based on time varying modelSaber Izadpanah Tous, E. Mohamadi, M. Mousavi, R. Darvish Khalil Abadi, Ehsan Kargaran, Hooman Nabovati. 274-277 [doi]
• Lightweight benchmarking of platforms for network traffic processingPavol Korcek, Martin Zádník. 278-283 [doi]
• A new analog output buffer for data driver of active matrix displays using low-temperature polycrystalline silicon thin-film transistorsIlias Pappas, Stilianos Siskos, Alkis A. Hatzopoulos. 284-287 [doi]
• Combining on-line fault detection and logic self repairTobias Koal, Markus Ulbricht, Heinrich Theodor Vierhaus. 288-293 [doi]
• Online self-checking and correction for crosstalk-induced timing errors on VLSI interconnectsPing-Liang Lai, Der-Chen Huang. 294-299 [doi]
• On test time reduction using pattern overlapping, broadcasting and on-chip decompressionMartin Chloupek, Ondrej Novák, Jiri Jenícek. 300-305 [doi]
• A SBST strategy to test microprocessors' Branch Target BufferPaolo Bernardi, Lyl M. Ciganda, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda. 306-311 [doi]
• An adaptive self-test routine for in-field diagnosis of permanent faults in simple RISC coresMario Schölzel, Tobias Koal, Heinrich Theodor Vierhaus. 312-317 [doi]
• CIVA: Custom instruction vulnerability analysis frameworkAli Azarpeyvand, Mostafa E. Salehi, Seid Mehdi Fakhraie. 318-323 [doi]
• Automated debugging from pre-silicon to post-siliconMehdi Dehbashi, Görschwin Fey. 324-329 [doi]
• On the use of assertions for embedded-software dynamic verificationGiuseppe Di Guglielmo, Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli. 330-335 [doi]
• Test platform for fault tolerant systems design properties verificationMartin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek. 336-341 [doi]
• Reliability challenges in avionics due to silicon agingBehzad Mesgarzadeh, Ingemar Söderquist Saab, Atila Alvandpour. 342-347 [doi]
• BTI impact on logical gates in nano-scale CMOS technologySeyab Khan, Said Hamdioui, Halil Kukner, Praveen Raghavan, Francky Catthoor. 348-353 [doi]
• On-chip aging sensor to monitor NBTI effect in nano-scale SRAMArthur Ceratti, Thiago Copetti, Letícia Maria Bolzani Poehls, Fabian Vargas. 354-359 [doi]
• Complementary edge alignment and digital output signal speed-up CMOS positive feedback latchesVladimir Milovanovic, Horst Zimmermann. 360-365 [doi]
• Reconfigurable time interval measurement circuit incorporating a programmable gain time difference amplifierAhmed Naif M. Alahmadi, Gordon Russell, Alex Yakovlev. 366-371 [doi]
• Efficient digital design for automotive mixed-signal ASICs using simulinkAndreas Mauderer, Marvin Freier, Jan-Hendrik Oetjens, Wolfgang Rosenstiel. 372-377 [doi]
• VARMA - VARiability modelling and analysis toolGordon Russell, Frank P. Burns, Alex Yakovlev. 378-383 [doi]