Abstract is missing.
- Reliable Network-on-Chip Using a Low Cost Unequal Error Protection CodeAvijit Dutta, Nur A. Touba. 3-11 [doi]
- Fault Tolerant Source Routing for Network-on-ChipYoung Bok Kim, Yong-Bin Kim. 12-20 [doi]
- Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault ModeArmin Alaghi, Naghmeh Karimi, Mahshid Sedghi, Zainalabedin Navabi. 21-30 [doi]
- Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial ReconfigurabilityAbderrahim Doumar, Kentaroh Katoh, Hideo Ito. 31-40 [doi]
- Estimating Error Propagation Probabilities with Bounded VariancesHossein Asadi, Mehdi Baradaran Tahoori, Chandra Tirumurti. 41-49 [doi]
- A Refined Electrical Model for Particle Strikes and its Impact on SEU PredictionSybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube. 50-58 [doi]
- Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity ModelRani S. Ghaida, Payman Zarkesh-Ha. 59-67 [doi]
- SET Emulation Under a Quantized Delay ModelMario García-Valderas, Raúl Fernández Cardenal, Celia López-Ongil, Marta Portela-García, Luis Entrena. 68-77 [doi]
- Sensitivity Evaluation of TMR-Hardened Circuits to Multiple SEUs Induced by Alpha Particles in Commercial SRAM-Based FPGAsAndrea Manuzzato, Paolo Rech, Simone Gerardin, Alessandro Paccagnella, Luca Sterpone, Massimo Violante. 79-86 [doi]
- TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAsCristiana Bolchini, Antonio Miele, Marco D. Santambrogio. 87-95 [doi]
- Optimization of Self Checking FIR filters by means of Fault Injection AnalysisSalvatore Pontarelli, Luca Sterpone, Gian-Carlo Cardarilli, Marco Re, Matteo Sonza Reorda, Adelio Salsano, Massimo Violante. 96-104 [doi]
- Evaluation of Single Event Upset Mitigation Schemes for SRAM Based FPGAs Using the FLIPPER Fault Injection PlatformMonica Alderighi, Fabio Casini, Sergio D Angelo, Marcello Mancini, Sandro Pastore, Giacomo R. Sechi, Roland Weigand. 105-113 [doi]
- A Functional Verification Based Fault Injection EnvironmentAlfredo Benso, Alberto Bosio, Stefano Di Carlo, Riccardo Mariani. 114-122 [doi]
- Comparing fail-safe microcontroller architectures in light of IEC 61508Riccardo Mariani, Peter Fuhrmann. 123-131 [doi]
- A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems-On-ChipGiovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto. 132-141 [doi]
- A Defect-Tolerant Molecular-Based Memory ArchitectureYoon-Hwa Choi, Myeong-Hyeon Lee. 143-151 [doi]
- Checker Design for On-line Testing of Xilinx FPGA Communication ProtocolsMartin Straka, Jiri Tobola, Zdenek Kotásek. 152-160 [doi]
- Defect-Tolerant Gate Macro Mapping & Placement in Clock-Free Nanowire Crossbar ArchitectureRavi Bonam, Yong-Bin Kim, Minsu Choi. 161-169 [doi]
- Delay Fault Detection Problems in Circuits Featuring a Low Combinational DepthMichele Favalli. 170-178 [doi]
- Empirical Analysis of the Dependence of Test Power, Delay, Energy and Fault Coverage on the Architecture of LFSR-Based TPGsMehdi Kamal, Somayyeh Koohi, Shaahin Hessabi. 179-187 [doi]
- Fault Tolerant Arithmetic Operations with Multiple Error Detection and CorrectionMojtaba Valinataj, Saeed Safari. 188-196 [doi]
- Production Yield and Self-Configuration in the Future Massively Defective NanochipsPiotr Zajac, Jacques Henri Collet. 197-205 [doi]
- Test Generation for Single and Multiple Stuck-at Faults of a Combinational Circuit Designed by Covering Shared ROBDD with CLBsAnjela Matrosova, Ekaterina Loukovnikova, Sergei Ostanin, Alexandra Zinchuk, Ekaterina Nikoleva. 206-214 [doi]
- Testing of Asynchronous NULL Conventional Logic (NCL) Circuits in Synchronous-Based DesignWaleed Al-Assadi, Sindhu Kakarla. 215-222 [doi]
- Timing-Aware Diagnosis for Small Delay DefectsTakashi Aikyo, Hiroshi Takahashi, Yoshinobu Higami, Junichi Ootsu, Kyohei Ono, Yuzo Takamatsu. 223-234 [doi]
- A-Diagnosis: A Complement to Z-DiagnosisIrith Pomeranz, Sudhakar M. Reddy. 235-242 [doi]
- Test Generation and Diagnostic Test Generation for Open Faults with Considering Adjacent LinesHiroshi Takahashi, Yoshinobu Higami, Toru Kikkawa, Takashi Aikyo, Yuzo Takamatsu, Hiroyuki Yotsuyanagi, Masaki Hashizume. 243-251 [doi]
- Analysis of Specified Bit Handling Capability of Combinational Expander NetworksAbhijit Jas, Srinivas Patil. 252-260 [doi]
- Reduction of Fault Latency in Sequential Circuits by using DecompositionIlya Levin, Benjamin Abramov, Vladimir Ostrovsky. 261-271 [doi]
- Soft Error Hardening for Asynchronous CircuitsWeidong Kuang, Casto Manuel Ibarra, Peiyi Zhao. 273-281 [doi]
- Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault TestingTakashi Ikeda, Kazuteru Namba, Hideo Ito. 282-290 [doi]
- An Effective Approach for the Diagnosis of Transition-Delay Faults in SoCs, based on SBST and Scan ChainsJorge Luis Lagos-Benites, Davide Appello, Paolo Bernardi, Michelangelo Grosso, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda. 291-300 [doi]
- Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature VariationsJorge Semião, Juan J. Rodríguez-Andina, Fabian Vargas, Marcelino Bicho Dos Santos, Isabel C. Teixeira, João Paulo Teixeira. 303-311 [doi]
- RAM-Based Fault Tolerant State Machines for FPGAsLaura Frigerio, Fabio Salice. 312-320 [doi]
- Spare Parts in Analog Circuits: A Filter ExampleErik Schüler, Adão Antônio de Souza Jr., Luigi Carro. 321-329 [doi]
- A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy SchemaSwapnil Bahl. 331-339 [doi]
- Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM MemoriesCostas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan. 340-348 [doi]
- Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare DisksHaruhiko Kaneko, Eiji Fujiwara. 349-358 [doi]
- Lazy Error Detection for Microprocessor Functional UnitsMahmut Yilmaz, Albert Meixner, Sule Ozev, Daniel J. Sorin. 361-369 [doi]
- Effective Checkpoint and Rollback Using Hardware/OS CollaborationMichele Portolan, Régis Leveugle. 370-378 [doi]
- On-Line Periodic Self-Testing of High-Speed Floating-Point Units in MicroprocessorsGeorge Xenoulis, Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis. 379-387 [doi]
- A Scalable Framework for Defect Isolation of DNA Self-assemlbled NetworksMasaru Fukushi, Susumu Horiguchi, Luke Demoracski, Fabrizio Lombardi. 391-399 [doi]
- Error Tolerance of DNA Self-Healing Assemblies by PuncturingMasoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi. 400-408 [doi]
- Fault Secure Encoder and Decoder for Memory ApplicationsHelia Naeimi, André DeHon. 409-417 [doi]
- Safety Evaluation of NanoFabricsMichelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda. 418-426 [doi]
- Nanofabric PLA architecture with Redundancy EnhancementMandar V. Joshi, Waleed Al-Assadi. 427-435 [doi]
- Hierarchical Fault Compatibility Identification for Test Generation with a Small Number of Specified BitsStelios Neophytou, Maria K. Michael. 439-447 [doi]
- High Quality Test Vectors for Bridging Faults in the Presence of IC s Parameters VariationsMichele Favalli, Marcello Dalpasso. 448-456 [doi]
- Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical CircuitsIrith Pomeranz, Sudhakar M. Reddy. 457-455 [doi]
- Testing Reversible One-Dimensional QCA Arrays for Multiple FaultsJing Huang, Xiaojun Ma, Cecilia Metra, Fabrizio Lombardi. 469-477 [doi]
- Probabilistic Analysis of a Molecular Quantum-Dot Cellular Automata AdderTimothy J. Dysart, Peter M. Kogge. 478-486 [doi]
- On the Error Effects of Random Clock Shifts in Quantum-Dot Cellular Automata CircuitsMarco Ottavi, Hamid Hashempour, Vamsi Vankamamidi, Faizal Karim, Konrad Walus, André Ivanov. 487-495 [doi]
- Evaluation of Register-Level Protection Techniques for the Advanced Encryption Standard by Multi-Level Fault InjectionsPaolo Maistri, Pierre Vanhauwaert, Régis Leveugle. 499-507 [doi]
- Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection CircuitsFrancesco Regazzoni, Thomas Eisenbarth, Johann Großschädl, Luca Breveglieri, Paolo Ienne, Israel Koren, Christof Paar. 508-516 [doi]
- A Fault-Tolerant Active Pixel Sensor to Correct In-Field Hot Pixel DefectsJozsef Dudas, Michelle L. La Haye, Jenny Leung, Glenn H. Chapman. 517-525 [doi]
- Quantitative Analysis of In-Field Defects in Image Sensor ArraysJenny Leung, Jozsef Dudas, Glenn H. Chapman, Israel Koren, Zahava Koren. 526-534 [doi]