Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories

Costas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan. Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. In Cristiana Bolchini, Yong-Bin Kim, Adelio Salsano, Nur A. Touba, editors, 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy. pages 340-348, IEEE Computer Society, 2007. [doi]

Abstract

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