Table of Contents

• Eccentric SoC Architectures as the Future NormGordon J. Brebner. 2-9 [doi]
• NoCs: A new Contract between Hardware and SoftwareAxel Jantsch. 10-16 [doi]
• Towards the Digitally Named World -Challenges for New Social Infrastructures based on Information TechnologiesHiroto Yasuura. 17-22 [doi]
• Distance-aware L2 Cache Organizations for Scalable Multiprocessor SystemsSung Woo Chung, Hyong-Shik Kim, Chu Shik Jhon. 24-32 [doi]
• Unified Dual Data CachesBen H. H. Juurlink. 33-40 [doi]
• CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip MultiprocessorsLin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif. 41-49 [doi]
• Reversible Logic Synthesis for Minimization of Full-Adder CircuitHafiz Md. Hasan Babu, Md. Rafiqul Islam, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury. 50-54 [doi]
• Scheduling and Assignment for Real-time Embedded Systems with Resource ContentionLoïc Pontani, Denis Dupont. 55-61 [doi]
• Multi Component Digital Circuit Optimization by Solving FSM EquationsNina Yevtushenko, Svetlana Zharikova, Maria Vetrova. 62-69 [doi]
• DYNORA: A New Caching TechniqueP. Srivatsan, P. B. Sudarshan, P. P. Bhaskaran. 70-75 [doi]
• A Quadruple Precision and Dual Double Precision Floating-Point MultiplierAhmet Akkas, Michael J. Schulte. 76-81 [doi]
• Causality Constraints for Processor Architectures with Sub-Word ParallelismRainer Schaffer, Renate Merker, Francky Catthoor. 82-89 [doi]
• A methodology for the design of AHB bus master wrappersMarc Bertola, Guy Bois. 90-97 [doi]
• A Constructive Algorithm with Look-Ahead for Mapping and Scheduling of Task Graphs with Conditional EdgesWinthir Brunnbauer, Thomas Wild, Jürgen Foag, Nuria Pazos. 98-103 [doi]
• An Application of Functional Decomposition in ROM-Based FSM Implementation in FPGA DevicesMariusz Rawski, Henry Selvaraj, Tadeusz Luba. 104-111 [doi]
• Variations on Truncated MultiplicationJames E. Stine, Oliver M. Duverne. 112-119 [doi]
• Exploring Storage Organization in ASIP SynthesisManoj Kumar Jain, M. Balakrishnan, Anshul Kumar. 120-127 [doi]
• RDSP: A RISC DSP based on Residue Number SystemRicardo Chaves, Leonel Sousa. 128-137 [doi]
• Operating Region Modelling of Deep-submicron CMOS Buffers Driving Global Scope Inductive InterconnectsGregorio Cappuccino. 138-143 [doi]
• A Scheduling and Partitioning Scheme for Low Power Circuit Operating at Multiple VoltagesLing Wang, Henry Selvaraj. 144-147 [doi]
• Information-driven Library-based Circuit SynthesisLech Józwiak, Szymon Bieganski, Artur Chojnacki. 148-157 [doi]
• Low-power Branch Target Buffer for Application-Specific Embedded ProcessorsPeter Petrov, Alex Orailoglu. 158-165 [doi]
• A Communication Model Based on an n-Dimensional Torus Architecture Using Deadlock-Free Wormhole RoutingPhilip K. F. Hölzenspies, Erik Schepers, Wouter Bach, Mischa Jonker, Bart Sikkes, Gerard J. M. Smit, Paul J. M. Havinga. 166-172 [doi]
• A Development and Simulation Environment for a Floating Point Operations FPGA Based AcceleratorMarco Bera, Giovanni Danese, Ivo De Lotto, Francesco Leporati, Alvaro Spelgatti. 173-179 [doi]
• A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip ArchitectureTang Lei, Shashi Kumar. 180-189 [doi]
• A Novel Specification Model for IP-based DesignStephan Klaus, Sorin A. Huss. 190-196 [doi]
• An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC ArchitecturesGeorge Kornaros, Theofanis Orphanoudakis, Nicholaos Zervos. 197-205 [doi]
• Design and FPGA Implementation of a Video Scalar with on-chip reduced memory utilizationS. Ramachandran, S. Srinivasan. 206-213 [doi]
• Estimating the Utilization of Embedded FPGA Co-ProcessorYang Qu, Juha-Pekka Soininen. 214-221 [doi]
• A Dynamically Reconfigurable Accelerator for Operations over Boolean and Ternary VectorsValery Sklyarov, Iouliia Skliarova, Arnaldo Oliveira, António de Brito Ferrari. 222-229 [doi]
• Fast Heuristics for the Edge Coloring of Large GraphsMario Hilgemeier, Nicole Drechsler, Rolf Drechsler. 230-239 [doi]
• Back-End Dynamic Resource Allocation Heuristics for Power-Aware High-Performance Clustered ArchitecturesAmirali Baniasadi. 240-247 [doi]
• NOAH, a tool for argument reduction, serial and parallel decomposition of decision tablesMichal Pleban, Hubert Niewiadomski, Piotr Buciak, Henry Selvaraj, Piotr Sapiecha, Tadeusz Luba. 248-254 [doi]
• Design Tools and Reusable Libraries for FPGA-Based Digital CircuitsValery Sklyarov, Iouliia Skliarova, Pedro Almeida, Manuel Almeida. 255-263 [doi]
• HW/SW Codesign Incorporating Edge Delays Using Dynamic ProgrammingKarthikeyan Bhasyam, Kia Bazargan. 264-271 [doi]
• Reconfigurable Randomized K-way Graph PartitioningFatih Kocan. 272-278 [doi]
• Multiple Voltage and Frequency Scheduling for Power MinimizationBharath Radhakrishnan, Muthukumar Venkatesan. 279-285 [doi]
• A Fast Additive Normalization Method for Exponential ComputationChichyang Chen, Rui-Lin Chen, Ming-Hwa Sheu. 286-293 [doi]
• A VLIW Architecture for Logarithmic ArithmeticMark G. Arnold. 294-303 [doi]
• Testable Design Verification Using Petri NetsRichard Ruzicka. 304-311 [doi]
• Hierarchical Constraint Conscious RT-level Test GenerationOzgur Sinanoglu, Alex Orailoglu. 312-318 [doi]
• A System-on-Chip Implementation of the IEEE 802.11a MAC LayerGoran Panic, Daniel Dietterle, Zoran Stamenkovic, Klaus Tittelbach-Helmrich. 319-324 [doi]
• The Application of Formal Verification to SPW DesignsBehzad Akbarpour, Sofiène Tahar. 325-333 [doi]
• Successful Prototyping of a Real-Time Hardware Based Terrain Navigation Correlator AlgorithmFilip Traugott, Kim Andersson, Andreas Löfgren, Lennart Lindh. 334-337 [doi]
• A New Algorithm for High-Speed Projection in Point Rendering ApplicationsMargarita Amor, Montserrat Bóo, Ángel del Río, Michael Wand, Wolfgang Straßer. 338-345 [doi]
• Sensor Platform Design for Automotive ApplicationsMarco De Marinis, Luca Fanucci, A. Giambastiani, Alessandro Renieri, A. Rocchi, Christian Rosadini, Claudio Sicilia, Daniele Sicilia. 346-355 [doi]
• Modelling and Simulation of a Digital IC System Using SimulPet: Application to a Speech Coding Communication ICR. Fernández-Ramos, J. Romero-Sánchez, F. Ríos-Gómez, J. Martín-Canales. 356-361 [doi]
• T&D-Bench+ - A Software Environment for Modeling and Simulation of State-of-the-Art ProcessorsSandro Neves Soares, Flávio Rech Wagner. 362-369
• Back-Traced Deductive-Parallel Fault Simulation for Digital SystemsVladimir Hahanov, Raimund Ubar, Stanley Hyduke. 370-377 [doi]
• Temperature Influence on Power Consumption and Time DelayAdam Golda, Andrzej Kos. 378-383 [doi]
• A Real Time, Low Latency, FPGA Implementation of the 2-D Discrete Wavelet Transformation for Streaming Image ApplicationsO. Benderli, Yusuf Çagatay Tekmen, A. Neslin Ismailoglu. 384-391 [doi]
• Understanding Video Pixel Processing Applications for Flexible ImplementationsOm Prakash Gangwal, Johan Janssen, Selliah Rathnam, Erwin B. Bellers, Marc Duranton. 392-401 [doi]
• Power/Area Analysis and Optimization of a DS-SS receiver for an Integrated Sensor MicrosystemNizamettin Aydin, Tughrul Arslan, David R. S. Cumming. 402-407 [doi]
• A Power Reduction Scheme for Data Buses by Dynamic Detection of Active BitsMasanori Muroyama, Akihiko Hyodo, Takanori Okuma, Hiroto Yasuura. 408-415 [doi]
• Framed Complexity Analysis in SystemC for Multi-level Design Space ExplorationArmin Wellig, Julien Zory. 416-425 [doi]
• Analytical Bounds on the Threads in IXP1200 Network ProcessorS. T. G. S. Ramakrishna, H. S. Jamadagni. 426-429 [doi]
• Concurrent Operation Scheduling and Unit Allocation with an Evolutionary TechniqueGregor Papa, Jurij Silc. 430-433 [doi]
• Exact Numerical ProcessingJuan Manuel García Chamizo, Jerónimo Mora Pascual, Higinio Mora Mora. 434-437 [doi]
• Stochastic Reconfigurable Hardware for Neural NetworksNadia Nedjah, Luiza de Macedo Mourelle. 438-442 [doi]
• An Iterative Improvement Co-synthesis Algorithm for Optimization of SOPC Architecture with Dynamically Reconfigurable FPGAsRadoslaw Czarnecki, Stanislaw Deniziak, Krzysztof Sapiecha. 443-446 [doi]
• Distributing SoC Simulations over a Network of ComputersJouni Riihimäki, Väinö Helminen, Kimmo Kuusilinna, Timo D. Hämäläinen. 447-450 [doi]
• FC-Min: A Fast Multi-Output Boolean MinimizerPetr Fiser, Jan Hlavicka, Hana Kubatova. 451-454 [doi]
• A Methodology for Designing Communication Architectures for Multiprocessor SoCsVaclav Dvorak, Vladimír Kutálek. 455-458 [doi]
• Compiler-Directed Management of Instruction AccessesGuangyu Chen, Ismail Kadayif, Wei Zhang 0002, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer. 459-462 [doi]
• Test scheduling for embedded systemsZdenek Kotásek, Daniel Mika, Josef Strnadel. 463-467 [doi]
• Customizable Embedded Processor ArchitecturesPeter Petrov, Alex Orailoglu. 468-475 [doi]