Table of Contents

• Code is Ethics - Formal Techniques for a Better WorldRolf Drechsler, Christoph Lüth. 1-3 [doi]
• GRanDE: Graphical Representation and Design Space Exploration of Embedded SystemsRajesh Kedia, M. Balakrishnan, Kolin Paul. 4-12 [doi]
• MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic AlgorithmPinar Kullu, Suleyman Tosun. 13-18 [doi]
• Multi-sensor Energy Efficient Obstacle DetectionAnupam Sobti, M. Balakrishnan, Chetan Arora 0001. 19-26 [doi]
• A Microprogrammed Approach for Implementing StatechartsJavier Cereijo García, Roberto Osorio. 27-34 [doi]
• AEx: Automated Customization of Exposed Datapath Soft-CoresAlex Hirvonen, Kati Tervo, Heikki Kultala, Pekka Jääskeläinen. 35-42 [doi]
• A Hardware Accelerator for Edge Detection in High-Definition Video using Cellular Neural NetworksIgnacio Pérez, Wladimir E. Valenzuela, Miguel Figueroa. 43-50 [doi]
• An RTL ATPG Flow Using the Gate Inherent Fault (GIF) Model Applied on Non-, Standard- and Random-Access-Scan (RAS)Tobias Strauch. 51-60 [doi]
• MicroLET: A New SDNoC-Based Communication Protocol for ChipLET-Based SystemsSoultana Ellinidou, Gaurav Sharma 0006, Sotirios Kontogiannis, Olivier Markowitch, Jean-Michel Dricot, Guy Gogniat. 61-68 [doi]
• Real-Time Textureless-Region Tolerant High-Resolution Depth Estimation SystemBilal Demir, Jean-Philippe Thiran, Yusuf Leblebici. 69-73 [doi]
• SAT-Hard: A Learning-Based Hardware SAT-SolverBuse Ustaoglu, Sebastian Huhn 0001, Frank Sill Torres, Daniel Große, Rolf Drechsler. 74-81 [doi]
• A Reconfigurable Architecture for Posit ArithmeticSouradip Sarkar, Purushotham Murugappa, Manil Dev Gomony. 82-87 [doi]
• Odyn: Deadlock Prevention and Hybrid Scheduling Algorithm for Real-Time Dataflow ApplicationsBenjamin Dauphin, Renaud Pacalet, Andrea Enrici, Ludovic Apvrille. 88-95 [doi]
• Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy ControllerOana Boncalo, Alexandru Amaricai, Zsófia Lendek. 96-101 [doi]
• Live State-of-Health Safety Monitoring for Safety-Critical Automotive SystemsAndreas Strasser, Philipp Stelzer, Christian Steger, Norbert Druml. 102-107 [doi]
• Enabling Cognitive Autonomy on Small Drones by Efficient On-Board Embedded Computing: An ORB-SLAM2 Case StudyErqian Tang, Sobhan Niknam, Todor P. Stefanov. 108-115 [doi]
• EVC-Based Power Gating Approach to Achieve Low-Power and High Performance NoCPeng Wang 0036, Sobhan Niknam, Sheng Ma, Zhiying Wang, Todor P. Stefanov. 116-123 [doi]
• Design of a SystemVerilog-Based Sigma-Delta ADC Real Number ModelConstantina Tsechelidou, Nikolaos Georgoulopoulos, Alkiviadis A. Hatzopoulos. 124-128 [doi]
• Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic AgentsTim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Große, Rolf Drechsler. 129-136 [doi]
• An Open-Source High-Throughput, Reduced Memory Footprint, Face Detection, Pose Estimation and Landmark Localization SystemPanos Kalodimas, Antonis Nikitakis, Ioannis Papaefstathiou. 137-143 [doi]
• Improving Digital Circuit Simulation with Batch-Parallel Logic EvaluationMaria Patrou, Jean-Philippe Legault, Aaron Graham, Kenneth B. Kent. 144-151 [doi]
• DSD-i1: A Mixed Functionality Development Board Geared Towards Digital Systems Design EducationAnastasios Fanariotis, Theofanis Orphanoudakis, Vasilios Fotopoulos, Paris Kitsos. 152-159 [doi]
• The Conical-Fishbone Clock Tree: A Clock-Distribution Network for a Heterogeneous Chip Multiprocessor AI ChipletTomas Figliolia, Andreas G. Andreou. 160-165 [doi]
• Combined Compression of Multiple Correlated Data Streams for Online-Diagnosis SystemsSeungbum Jo, Markus Lohrey, Simon Meckel, Roman Obermaisser, Simon Plasger. 166-173 [doi]
• Design of Novel CMOS Based Inexact Subtractors and Dividers for Approximate Computing: An In-Depth Comparison with PTL Based DesignsChandan Kumar Jha, Joycee Mekie. 174-181 [doi]
• Generating Efficient Parallel Code from the RVC-CAL Dataflow LanguageOmair Rafique, Florian Krebs, Klaus Schneider 0001. 182-189 [doi]
• Novel Approximate Absolute Difference HardwareAhmet Can Mert, Hasan Azgin, Ercan Kalali, Ilker Hamzaoglu. 190-193 [doi]
• An Efficient FPGA Implementation of Versatile Video Coding Intra PredictionHasan Azgin, Ercan Kalali, Ilker Hamzaoglu. 194-199 [doi]
• Occupancy Grid Fusion of Low-Level Radar and Time-of-Flight Sensor DataJosef Steinbaeck, Christian Steger, Eugen Brenner, Gerald Holweg, Norbert Druml. 200-205 [doi]
• Analyzing the Impact of Probabilistic Estimates on Communication Reliability at Intelligent CrossroadsDaniel Markert, Philip Parsch, Alejandro Masrur. 206-213 [doi]
• On the Bright Side of Darkness: Side-Channel Based Authentication Protocol Against Relay AttacksGuillaume Dabosville, Houssem Maghrebi, Alexis Lhuillery, Thanh-Ha Le, Julien Bringer. 214-221 [doi]
• Circumventing Uniqueness of XOR Arbiter PUFsCaio Hoffman, Catherine H. Gebotys, Diego F. Aranha, Mario L. Côrtes, Guido Araújo. 222-229 [doi]
• Toward a Hardware Man-in-the-Middle Attack on PCIe Bus for Smart Data ReplayMohamed Amine Khelif, Jordane Lorandel, Olivier Romain, Matthieu Regnery, Denis Baheux, Guillaume Barbu. 230-237 [doi]
• Authenticated Encryption Schemes on Java CardRajesh Kumar Pal. 238-245 [doi]
• Application Study of Hardware-Based Security for Future Industrial IoTRainer Matischek, Benjamin Bara. 246-252 [doi]
• Design and Implementation of a Fast and Scalable NTT-Based Polynomial Multiplier ArchitectureAhmet Can Mert, Erdinç Öztürk, Erkay Savas. 253-260 [doi]
• Deep Learning Side-Channel Attack Against Hardware Implementations of AESTakaya Kubota, Kota Yoshida, Mitsuru Shiozaki, Takeshi Fujino. 261-268 [doi]
• LAOCOÖN: A Run-Time Monitoring and Verification Approach for Hardware Trojan DetectionJean-Luc Danger, Laurent Fribourg, Ulrich Kühne, Maha Naceur. 269-276 [doi]
• Dynamic Logic Reconfiguration Based Side-Channel Protection of AES and SerpentPetr Socha, Jan Brejník, Stanislav Jerabek, Martin Novotný, Nele Mentens. 277-282 [doi]
• Device Driver and System Call Isolation in Embedded DevicesMaja Malenko, Marcel Baunach. 283-290 [doi]
• Information Coding and Hardware Architecture of Spiking Neural NetworksNassim Abderrahmane, Benoît Miramond. 291-298 [doi]
• Graphical Model Transformation Analysis for Cognitive Computing and Machine Learning on the SpiNNaker Chip MultiprocessorAndreas G. Andreou, Daniel R. Mendat. 299-304 [doi]
• TOT-Net: An Endeavor Toward Optimizing Ternary Neural NetworksNajmeh Nazari, Mohammad Loni, Mostafa E. Salehi, Masoud Daneshtalab, Mikael Sjödin. 305-312 [doi]
• Keyword Spotting using Time-Domain Features in a Temporal Convolutional NetworkEmad A. Ibrahim, Jos Huisken, Hamed Fatemi, José Pineda de Gyvez. 313-319 [doi]
• Testability of Switching Lattices in the Cellular Fault ModelAnna Bernasconi 0001, Valentina Cieiani, Luca Frontini. 320-327 [doi]
• PoLibSi: Path Towards Intrinsically Reconfigurable ComponentsJan Nevoral, Václav Simek, Richard Ruzicka. 328-334 [doi]
• PAIG Rewriting: The Way to Scalable Multifunctional Digital Circuits SynthesisAdam Crha, Václav Simek, Richard Ruzicka. 335-342 [doi]
• An Application of Hyper-Heuristics to Flexible Manufacturing SystemsAlexis Linard, Joost van Pinxten. 343-350 [doi]
• Leveraging Domain Knowledge for the Efficient Design-Space Exploration of Advanced Cyber-Physical SystemsYon Vanommeslaeghe, Joachim Denil, Jasper De Viaene, David Ceulemans, Stijn Derammelaere, Paul De Meulenaere. 351-358 [doi]
• Enhancing Battery Pack Capacity Utilization in Electric Vehicle Fleets via SoC-PreconditioningAlexander Lamprecht, Ananth Garikapati, Swaminathan Narayanaswamy, Sebastian Steinhorst. 359-364 [doi]
• System Performance Modelling of Heterogeneous HW Platforms: An Automated Driving Case StudyFalk Wurst, Dakshina Dasari, Arne Hamann, Dirk Ziegenbein, Ignacio Sañudo, Nicola Capodieci, Marko Bertogna, Paolo Burgio. 365-372 [doi]
• On Analyzing Memory Latency for Embedded CPS PlatformsSelma Saidi. 373-380 [doi]
• CMOS Illumination Discloses Processed DataJan Belohoubek, Petr Fiser, Jan Schmidt. 381-388 [doi]
• PRYSTINE - Technical Progress After Year 1Norbert Druml, Omar Veledar, Georg Macher, Georg Stettinger, Solmaz Selim, Jakob Reckenzaun, Sergio E. Diaz, Mauricio Marcano, Jorge Villagra, Rutger Beekelaar, Johannes Jany-Luig, Marta Maria Corredoira, Paolo Burgio, Christian Ballato, Björn Debaillie, Lars van Meurs, Andrei Sergeevich Terechko, Fabio Tango, Anna Ryabokon, Andrei Anghel, Oguz Icoglu, Sumeet S. Kumar, George Dimitrakopoulos. 389-398 [doi]
• GPU4S: Embedded GPUs in SpaceLeonidas Kosmidis, Jérôme Lachaize, Jaume Abella, Olivier Notebaert, Francisco J. Cazorla, David Steenari. 399-405 [doi]
• The CASPER Project Approach Towards User-Centric Mobile NetworksEirini Liotou, Dimitris Tsolkas, Stefano Tennina, Luigi Pomante, Giorgos Kalpaktsoglou, Nikos Passas. 406-413 [doi]
• The AFarCloud ECSEL ProjectPedro Castillejo, Baran Çürüklü, Roberto Fresco, Gorm Johansen, Sonia Bilbao-Arechabala, Belén Martínez Rodriguez, Luigi Pomante, José-Fernán Martínez-Ortega, Marco Santic. 414-419 [doi]
• Framework of Key Enabling Technologies for Safe and Autonomous Drones' ApplicationsRéda Nouacer, Huáscar Espinoza Ortiz, Yassine Ouhammou, Rodrigo Castiñeira González. 420-427 [doi]
• Challenges in Deeply Heterogeneous High Performance SystemsGiovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, Jose Flich, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater. 428-435 [doi]
• Smart Chair System for Posture CorrectionGeorge Flutur, Bogdan Movileanu, Lengyel Károly, Ionut Danci, Daniel Cosovanu, Ovidiu Petru Stan. 436-441 [doi]
• An IoT-Based Framework for Elderly Remote MonitoringIssam Boukhennoufa, Abbes Amira, Faycal Bensaali, Dimosthenis Anagnostopoulos, Mara Nikolaidou, Christos Kotronis, Elena Politis, George Dimitrakopoulos. 442-448 [doi]
• Optimization of CCOs with Implantable MEMS Pressure Sensors for Cardiovascular ApplicationsJose Angel Miguel, Yolanda Lechuga, Miguel Angel Allende, Mar Martínez. 449-455 [doi]
• Development of Cyber-Physical Speech-Controlled Wheelchair for Disabled PersonsAndrej Skraba, Andrej Kolozvari, Davorin Kofjac, Radovan Stojanovic, Eugene Semenkin, Vladimir Stanovov. 456-463 [doi]
• Automatic and Unsupervised Identification of Specific Biochemical Features from Raman Mapping DataEmanuele Torti, Beatrice Marcinnò, Renzo Vanna, Carlo Morasso, Francesca Picotti, Laura Villani, Francesco Leporati. 464-469 [doi]
• Accurate Inexact Calculations of Non-Homogeneous Markov ChainsJan Reznícek, Martin Kohlík, Hana Kubátová. 470-477 [doi]
• On Precise Fault Localization and Identification in NoC ArchitecturesMartin Stáva. 478-484 [doi]
• Local Monitoring of Embedded Applications and Devices using Artificial Neural NetworksFin Hendrik Bahnsen, Görschwin Fey. 485-491 [doi]
• True Path Tracing in Structurally Synthesized BDDs for Testability Analysis of Digital CircuitsRaimund Ubar, Lembit Jürimägi, Adeniyi Olanrewaju Adekoya, Maksim Jenihhin. 492-499 [doi]
• Combinational Decompressors with Nonlinear CodesOndrej Novák, Martin Rozkovec, Jan Pliva. 500-505 [doi]
• Testing Reliability of Smart Electronic Locks: Analysis and the First Steps TowardsOndrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek. 506-513 [doi]
• Design of SRAM-Based Low-Cost SEU Monitor for Self-Adaptive Multiprocessing SystemsJunchao Chen, Marko S. Andjelkovic, Aleksandar Simevski, Yuanqing Li, Patryk Skoncej, Milos Krstic. 514-521 [doi]
• Scalable Simulation-Based Verification of SystemC-Based Virtual PrototypesMehran Goli, Rolf Drechsler. 522-529 [doi]
• Consideration of Security Attacks in the Design Space Exploration of Embedded SystemsLukas Gressl, Christian Steger, Ulrich Neffe. 530-537 [doi]
• An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological BehaviorDavid Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 538-545 [doi]
• Online Peak Power and Maximum Temperature Management in Multi-core Mixed-Criticality Embedded SystemsBehnaz Ranjbar, Tuan D. A. Nguyen, Alireza Ejlali, Akash Kumar 0001. 546-553 [doi]
• HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW PartitionsVittoriano Muttillo, Luigi Pomante, Patricia Balbastre, José E. Simó, Alfons Crespo. 554-561 [doi]
• Structural Self-Adaptation for Decentralized Pervasive IntelligenceJovan Nikolic, Evangelos Pournaras. 562-571 [doi]
• System Design of an Open-Source Cloud-Based Framework for Internet of Drones ApplicationGolizheh Mehrooz, Emad Ebeid, Peter Schneider-Kamp. 572-579 [doi]
• A Survey on Multi-unmanned Aerial Vehicle Communications for Autonomous InspectionsLiping Shi, Nestor J. Hernandez Marcano, Rune Hylsberg Jacobsen. 580-587 [doi]
• The European H2020 project VESSEDIA (Verification Engineering of Safety and SEcurity critical Dynamic Industrial Applications)Armand Puccetti. 588-591 [doi]
• Model-Based Processor-in-the-Loop Framework for Composable Multi-core PlatformsMojtaba Haghi, Martijn Koedam, Dip Goswami, Kees Goossens. 592-596 [doi]
• Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case StudyJakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek. 597-600 [doi]
• Modeling the Impact of Process Variations in Worst-Case Energy Consumption EstimationDavid Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 601-605 [doi]
• Platform Independent Software Analysis for Near Memory ComputingStefano Corda, Gagandeep Singh, Ahsan Jawed Awan, Roel Jordans, Henk Corporaal. 606-609 [doi]
• Formal Verification Methodology in an Industrial SetupLorenzo Servadei, Zhao Han, Michael Werner, Wolfgang Ecker, Keerthikumara Devarajegowda. 610-614 [doi]
• Coded Modulation Simulation Framework for Time-of-Flight CamerasArmin Schoenlieb, Matthias Almer, David Lugitsch, Christian Steger, Gerald Holweg, Norbert Druml. 615-619 [doi]
• Reliability Assessment of Flooded Min-Sum LDPC Decoders Based on Sub-Threshold Processing UnitsSergiu Nimara. 620-623 [doi]
• A Very Compact Architecture of CLEFIA Block Cipher for Secure IoT SystemsLampros Pyrgas, Paris Kitsos. 624-627 [doi]
• A Study of Performance and Power Consumption Differences Among Different ISAsAyaz Akram, Lina Sawalha. 628-632 [doi]
• Side-Channel Attack on the A5/1 Stream CipherMartin Jurecek, Jirí Bucek, Róbert Lórencz. 633-638 [doi]
• Aspects on Timing Modeling of Radiation-Hardness by Design Standard Cell-Based △TMR Flip-FlopsOliver Schrape, Anselm Breitenreiter, Steffen Zeidler 0001, Milos Krstic. 639-642 [doi]
• High-Throughput BitPacking CompressionNusrat Jahan Lisa, Tuan Duy Anh Nguyen, Dirk Habich, Akash Kumar 0001, Wolfgang Lehner. 643-646 [doi]
• Design and Implementation of a Low-Power, Embedded CNN Accelerator on a Low-end FPGABahareh Khabbazan, Sattar Mirzakuchaki. 647-650 [doi]
• Fault Tolerant FPGAs: Where to Spend the Effort?Mahsa Mousavi, Sayandip De, Hamid Reza Pourshaghaghi, Henk Corporaal. 651-654 [doi]
• Analyzing the Impact of Secure CAN Networks on Braking Dynamics of Cooperative DrivingDharshan Krishna Murthy, Mingqing Zhang, Alejandro Masrur. 655-658 [doi]
• Hardware Acceleration of k-Mer Clustering using Locality-Sensitive HashingJavier E. Soto, Thomas Krohmer, Cecilia Hernández, Miguel Figueroa. 659-662 [doi]
• Bit-Shift-Based Accelerator for CNNs with Selectable Accuracy and ThroughputSebastian Vogel, Rajatha B. Raghunath, Andre Guntoro, Kristof Van Laerhoven, Gerd Ascheid. 663-667 [doi]
• Exploiting Emerging Reconfigurable Technologies for Secure DevicesAnsh Rupani, Shubham Rai, Akash Kumar 0001. 668-671 [doi]
• Design and Verification of Secure Cache Wrapper Against Access-Driven Side-Channel AttacksBehrad Niazmand, Siavoosh Payandeh Azad, Gert Jervan, Johanna Sepúlveda. 672-676 [doi]