Abstract is missing.
- Towards Efficient Field Programmable Pattern Matching ArrayVlastimil Kosar, Jan Korenek. 1-8 [doi]
- An FPGA Framework for Genetic Algorithms: Solving the Minimum Energy Broadcast ProblemPedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira. 9-16 [doi]
- Worst-Case Throughput Analysis of SDF-Based Parametrized DataflowMladen Skelin, Marc Geilen, Francky Catthoor, Sverre Hendseth. 17-24 [doi]
- A Scenario-Aware Dataflow Programming ModelReinier van Kampenhout, Sander Stuijk, Kees Goossens. 25-32 [doi]
- Integrating Task Migration Capability in Software Tool-Chain for Data-Flow Applications Mapped on Multi-tiled ArchitecturesAshraf El Antably, Nicolas Fournel, Frédéric Rousseau. 33-40 [doi]
- Hardware Support for Cost-Effective System-Level Protection in Multi-core SoCsGeorge Kornaros, Ioannis Christoforakis, Othon Tomoutzoglou, Dimitrios Bakoyiannis, Kallia Vazakopoulou, Miltos D. Grammatikakis, Antonis Papagrigoriou. 41-48 [doi]
- High-Level Synthesis Design Flow for HEVC Intra Encoder on SoC-FPGAPanu Sjovall, Janne Virtanen, Jarno Vanne, Timo D. Hämäläinen. 49-56 [doi]
- Accelerating Clifford Algebra Operations Using GPUs and an OpenCL Code GeneratorSilvia Franchini, Antonio Gentile, Giorgio Vassallo, Salvatore Vitabile. 57-64 [doi]
- Using Dynamic Reconfiguration to Reduce the Area of a JPEG Decoder on FPGATiago Rodrigues, Mário P. Véstias. 65-71 [doi]
- Bi-Decomposition Using Boolean RelationsAnna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa. 72-78 [doi]
- A Bundled-Data Asynchronous Circuit Synthesis Flow Using a Commercial EDA FrameworkMatheus Gibiluka, Matheus Trevisan Moreira, Ney Laert Vilar Calazans. 79-86 [doi]
- Automation and Optimization of Coverage-driven VerificationMarcela imkova, Zdenek Kotásek. 87-94 [doi]
- Investigation on AUTOSAR-Compliant Solutions for Many-Core ArchitecturesMatthias Becker, Dakshina Dasari, Vincent Nélis, Moris Behnam, Luís Miguel Pinho, Thomas Nolte. 95-103 [doi]
- Distributed Parallel Computing with Low Cost Microcontrollers for High Performance Electric VehiclesVictor Wilson Goncalves Azevedo, João Dionísio Simões Barros. 104-110 [doi]
- Harnessing Performance Variability: A HPC-Oriented Application ScenarioGiuseppe Massari, Simone Libutti, Antoni Portero, Radim Vavrík, Stepan Kuchar, Vít Vondrák, Luca Borghese, William Fornaciari. 111-116 [doi]
- The AXIOM Software LayersCarlos Álvarez, Eduard Ayguadé, Javier Bueno, Antonio Filgueras, Daniel Jiménez-González, Xavier Martorell, Nacho Navarro, Dimitris Theodoropoulos, Dionisios N. Pnevmatikatos, Davide Catani, Claudio Scordino, Paolo Gai, Carlos Segura, Carles Fernández, David Oro, Javier Rodríguez Saeta, Pierluigi Passera, Alberto Pomella, Antonio Rizzo, Roberto Giorgi. 117-124 [doi]
- EMC2 a Platform Project on Embedded Microcontrollers in Applications of Mobility, Industry and the Internet of ThingsWerner Weber, Alfred Hoess, Frank Oppenheimer, Bernd Koppenhoefer, Bastijn Vissers, Bjørn Nordmoen. 125-130 [doi]
- A Flexible Research Testbed for C-RANDiogo Riscado, Jorge Santos, Daniel Dinis, Gustavo Anjos, Daniel Belo, Nuno Borges Carvalho, Arnaldo S. R. Oliveira. 131-138 [doi]
- Reconfigurable Traffic-Aware Radio Interconnect for a 2048-core Chip MultiprocessorEren Unlu, Christophe Moy. 139-145 [doi]
- An Agile and Wideband All-Digital SDR Receiver for 5G Wireless CommunicationsAndre Prata, Arnaldo S. R. Oliveira, Nuno Borges Carvalho. 146-151 [doi]
- Enhanced Quality Using Intensive Test and Analysis on SimulatorsReda Nouacer, Manel Djemal, Smaïl Niar, Gilles Mouchard, Nicolas Rapin, Jean-Pierre Gallois, Philippe Fiani, Francois Chastrette, Toni Adriano, Bryan MacEachen. 152-157 [doi]
- Playful Supervised Smart Spaces (P3S) - A Framework for Designing, Implementing and Deploying Multisensory Play Experiences for Children with Special NeedsGiovanni Agosta, Luca Borghese, Carlo Brandolese, Francesco Clasadonte, William Fornaciari, Franca Garzotto, Mirko Gelsomini, Matteo Grotto, Cristina Frà, Danny Noferi, Massimo Valla. 158-164 [doi]
- Implantable MEMS Pressure Sensors Modelling ToolJose Angel Miguel, David Rivas, Yolanda Lechuga, Miguel Angel Allende, Mar Martínez. 165-172 [doi]
- Estimation of Blood Pressure and Pulse Transit Time Using Your SmartphoneAlair Dias Junior, Srinivasan Murali, Francisco J. Rincón, David Atienza. 173-180 [doi]
- Reliable and Continuous Measurement of SET Pulse WidthsVaradan Savulimedu Veeravalli, Andreas Steininger. 181-188 [doi]
- Measuring the Distribution of Metastable Upsets over TimeThomas Polzer, Andreas Steininger. 189-196 [doi]
- Generic Self Repair Architecture with Multiple Fault Handling CapabilityMarcel Baláz, Stefan Kristofik. 197-204 [doi]
- A System for Radiation Testing and Physical Fault Injection into the FPGAs and Other ElectronicsTomas Vanat, Jan Pospiil, Filip Kriek, Jozef Ferencei, Hana Kubatova. 205-210 [doi]
- Biconditional-BDD Ordering for Autosymmetric FunctionsAnna Bernasconi, Valentina Ciriani, Gabriella Trucco. 211-217 [doi]
- Enhanced Spin-Diode Synthesis Using Logic SharingMayler Martins, Felipe S. Marranghello, Joseph S. Friedman, Alan V. Sahakian, Renato P. Ribas, André Inácio Reis. 218-224 [doi]
- A Glimpse of SmartHG Project Test-bed and Communication InfrastructureVadim Alimguzhin, Federico Mari, Igor Melatti, Enrico Tronci, Emad Samuel Malki Ebeid, Søren Aagaard Mikkelsen, Rune Hylsberg Jacobsen, Jorn Klaas Gruber, Barry P. Hayes, Francisco Huerta, Milan Prodanovic. 225-232 [doi]
- Towards the Use of Pairing-Based Cryptography for Resource-Constrained Home Area NetworksRune Hylsberg Jacobsen, Søren Aagaard Mikkelsen, Niels Holm Rasmussen. 233-240 [doi]
- Distributed Grid Storage by Ordinary House Heating Variations: A Swiss Case StudyGilbert Maître, Gillian Basso, Claudio Steiner, Dominique Gabioud, Pierre Roduit. 241-249 [doi]
- Buffer Allocation for Dynamic Real-Time Streaming Applications Running on a Multi-processor without Back-PressureHrishikesh Salunkhe, Alok Lele, Orlando Moreira, Kees van Berkel. 250-254 [doi]
- A Framework for Dynamic Real-Time ReconfigurationJoao Gabriel Reis, Lucas Francisco Wanner, Antônio Augusto Fröhlich. 255-258 [doi]
- Minimization Method of Finite State Machines for Low Power DesignAdam Klimowicz, Valery Solov'ev, Tomasz Grzes. 259-262 [doi]
- Parameterizable Ethernet Network-on-Chip Architecture on FPGAHelio Fernandes da Cunha Junior, Bruno de Abreu Silva, Vanderlei Bonato. 263-266 [doi]
- Dynamic Detection and Mitigation of DMA Races in MPSoCsSelma Saidi, Ylies Falcone. 267-270 [doi]
- Green Computing: Power Optimisation of VFI-Based Real-Time Multiprocessor Dataflow ApplicationsWaheed Ahmad, Philip K. F. Hölzenspies, Mariëlle Stoelinga, Jaco van de Pol. 271-275 [doi]
- Low-Cost Fault Localization and Error Correction for a Signed Digit Adder Design Utilizing the Self-Dual ConceptHossein Moradian, Jeong-A. Lee. 276-279 [doi]
- Novel C-Element Based Error Detection and Correction Method Combining Time and Area RedundancyJan Belohoubek, Petr Fiser, Jan Schmidt. 280-283 [doi]
- Software Fault Tolerance: The Evaluation by Functional VerificationOndrej Cekan, Jakub Podivinsky, Zdenek Kotásek. 284-287 [doi]
- A Framework for Comprehensive Automated Evaluation of Concurrent Online CheckersPietro Saltarelli, Behrad Niazmand, Jaan Raik, Ranganathan Hariharan, Gert Jervan, Thomas Hollstein. 288-292 [doi]
- Safe Drive Map Concept for Road Curve MonitoringPietro DellAcqua, Francesco Bellotti, Riccardo Berta, Alessandro De Gloria, Gautam Dange, Pratheep Paranthaman, Kay Massow, Fabian Maximilian Thiele. 293-296 [doi]
- Information and Communication Technology Research Opportunities in Dynamic Charging for Electric VehicleOussama Smiai, Francesco Bellotti, Alessandro De Gloria, Riccardo Berta, Angelos Amditis, Yannis Damousis, Andrew Winder. 297-300 [doi]
- Consumer-Centric and Service-Oriented Architecture for the Envisioned Energy InternetSøren Aagaard Mikkelsen, Rune Hylsberg Jacobsen. 301-305 [doi]
- Experimental Evaluation and Modeling of Thermal Phenomena on Mobile DevicesMatteo Ferroni, Alessandro Antonio Nacci, Matteo Turri, Marco Domenico Santambrogio, Donatella Sciuto. 306-313 [doi]
- Exploiting Heterogeneity in Cache Hierarchy in Dark-Silicon 3D Chip Multi-processorsArghavan Asad, Ozcan Ozturk, Mahmood Fathy, Mohammad-Reza Jahed Motlagh. 314-321 [doi]
- Automated Design of High Performance Integer Arithmetic Cores on FPGAAyan Palchaudhuri, Rajat Subhra Chakraborty, Durga Prasad Sahoo. 322-329 [doi]
- Sparse Matrix Multiplication on a Reconfigurable Many-Core ArchitectureJoao Pinhao, Wilson Jose, Horácio C. Neto, Mário P. Véstias. 330-336 [doi]
- Computing Framework for Dynamic Integration of Reconfigurable Resources in a CloudOliver Knodel, Rainer G. Spallek. 337-344 [doi]
- Analysis and Comparison of Attainable Hardware Acceleration in All Programmable Systems-on-ChipValery Sklyarov, Iouliia Skliarova, João Silva, Alexander Sudnitson. 345-352 [doi]
- Unit-Based Functional IDDT Testing for Aging Degradation Monitoring in a VLIW ProcessorYong Zhao, Hans G. Kerkhoff. 353-358 [doi]
- Leveraging the Analysis for Invariant Independence in Formal System ModelsNils Przigoda, Robert Wille, Rolf Drechsler. 359-366 [doi]
- Collision Based Attacks in PracticeIbrahima Diop, Pierre-Yvan Liardet, Yanis Linge, Philippe Maurine. 367-374 [doi]
- Verification-Driven Design Across Abstraction Levels: A Case StudyNils Przigoda, Jannis Stoppe, Julia Seiter, Robert Wille, Rolf Drechsler. 375-382 [doi]
- A Low Power 64-point Bit-Serial FFT Engine for Implantable Biomedical ApplicationsLang Yang, Thomas W. Chen. 383-389 [doi]
- A Smart Mobile Lab-on-Chip-Based Medical Diagnostics System Architecture Designed for EvolvabilityFrancois Patou, Maria Dimaki, Winnie E. Svendsen, Klaus Kjaegaard, Jan Madsen. 390-398 [doi]
- Wireless Sensor Tag and Network for Improved Clinical TriageJoao Ricardo Borges dos Santos, Gabriel Blard, Arnaldo Silva Rodrigues Oliveira, Nuno Borges de Carvalho. 399-406 [doi]
- Towards Zero Bit-Error-Rate Physical Unclonable Function: Mismatch-Based vs. Physical-Based Approaches in Standard CMOS TechnologyDuhyun Jeon, Jong-Hak Baek, Dong Kyue Kim, Byong-Deok Choi. 407-414 [doi]
- Integrated Sensor: A Backdoor for Hardware Trojan Insertions?Xuan Thuy Ngo, Zakaria Najm, Shivam Bhasin, Debapriya Basu Roy, Jean-Luc Danger, Sylvain Guilley. 415-422 [doi]
- Side-Channel Leakage Models for RISC Instruction Set Architectures from Empirical DataHermann Seuschek, Stefan Rass. 423-430 [doi]
- Affine Coordinate Binary Edwards Curve Scalar Multiplier with Side Channel Attack ResistanceApostolos P. Fournaris, Odysseas G. Koufopavlou. 431-437 [doi]
- On-Line Device Replacement Techniques for SSD RAIDAlistair A. McEwan, Muhammed Ziya Komsul. 438-444 [doi]
- Gate Resizing for Soft Error Rate Reduction in Nano-scale Digital Circuits Considering Process VariationsMohsen Raji, Behnam Ghavami, Hossein Pedram. 445-452 [doi]
- Mixed-Criticality Embedded Systems - A Balance Ensuring Partitioning and PerformanceMichael Paulitsch, Oscar Medina Duarte, Hassen Karray, Kevin Mueller, Daniel Münch, Jan Nowotsch. 453-461 [doi]
- Enabling TDMA Arbitration in the Context of MBPTAMilos Panic, Jaume Abella, Carles Hernández, Eduardo Quiñones, Theo Ungerer, Francisco J. Cazorla. 462-469 [doi]
- SEMIAH: An Aggregator Framework for European Demand Response ProgramsRune Hylsberg Jacobsen, Dominique Gabioud, Gillian Basso, Pierre-Jean Alet, Armin Ghasem Azar, Emad Samuel Malki Ebeid. 470-477 [doi]
- User Flexibility Aware Price Policy Synthesis for Smart GridsToni Mancini, Federico Mari, Igor Melatti, Ivano Salvo, Enrico Tronci, Jorn Klaas Gruber, Barry Hayes, Milan Prodanovic, Lars Elmegaard. 478-485 [doi]
- An Extensible Simulator for Dynamic Control of Residential Area: Case Study on Heating ControlGillian Basso, Pierre Ferrez, Dominique Gabioud, Pierre Roduit. 486-493 [doi]
- Efficient Clustering of DERs in a Virtual Association for Profit OptimizationVasileios Botsis, Nikolaos D. Doulamis, Anastasios D. Doulamis, Prodromos Makris, Emmanouel A. Varvarigos. 494-501 [doi]
- Composable Platform-Aware Embedded Control Systems on a Multi-core ArchitectureJuan Valencia, Dip Goswami, Kees Goossens. 502-509 [doi]
- Low-Cost Software Control-Flow Error RecoveryGhazaleh Nazarian, Razvan Nane, Georgi Gaydadjiev. 510-517 [doi]
- Network-Aware Virtual Platform for the Verification of Embedded Software for CommunicationsCalypso Barnes, Jean-Marie Cottin, Davide Quaglia, Enrico Fraccaroli, Alain Pegatoquet, François Verdier, Stefano Angeleri. 518-525 [doi]
- Dataflow Support in x86_64 Multicore Architectures through Small Hardware ExtensionsAndrea Mondelli, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi. 526-529 [doi]
- QEMU-Based Fault Injection for a System-Level Analysis of Software Countermeasures Against Fault AttacksAndrea Höller, Armin Krieg, Tobias Rauter, Johannes Iber, Christian Kreiner. 530-533 [doi]
- White-Box Error Effect Simulation for Assisted Safety AnalysisSebastian Reiter, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel. 534-538 [doi]
- Parallel Native-Simulation for Multi-processing Embedded SystemsAlejandro Nicolas, Pablo Sanchez. 543-546 [doi]
- A Comparison of TERO and RO Timing Sensitivity for Hardware Trojan Detection ApplicationsParis Kitsos, Artemios G. Voyiatzis. 547-550 [doi]
- Clockwise Randomization of the Observable Behaviour of Crypto ASICs to Counter Side Channel AttacksZoya Dyka, Christian Wittke, Peter Langendörfer. 551-554 [doi]
- CLEFIA Implementation with Full Key ExpansionJoao Carlos Bittencourt, João Carlos Resende, Wagner Luiz de Oliveira, Ricardo Chaves. 555-558 [doi]
- Towards Ideal Arbiter PUF Design on Xilinx FPGA: A Practitioner's PerspectiveDurga Prasad Sahoo, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay. 559-562 [doi]
- Linking the Physical with the Perceptual: Health and Exposure Monitoring with Cyber-physical QuestionnairesChristopher Scaffidi, Laurel Kincl, Diana Rohlman, Kim Anderson. 563-566 [doi]
- Design for Dependability and Autonomy of a Wearable Cardiac and Coronary MonitorJosé Machado da Silva, Cristina Oliveira, Bruno Mendes, Ruben Dias, Tiago Marques. 567-570 [doi]
- A Modular Safety Case for an IEC-61508 Compliant Generic HypervisorAsier Larrucea, Jon Perez, Irune Agirre, Vicent Brocal, Roman Obermaisser. 571-574 [doi]
- An Embedded FTL for SSD RAIDAlistair A. McEwan, Irfan Mir. 575-582 [doi]
- Scalable FPGA Accelerator of the NRM Algorithm for Efficient Stochastic Simulation of Large-Scale Biochemical Reaction NetworksEvangelos Koutsouradis, George Provelengios, Elias Kouskoumvekakis, Elias S. Manolakos. 583-590 [doi]
- A Locality Aware Convolutional Neural Networks AcceleratorRunbin Shi, Zheng Xu, Zhihao Sun, Maurice Peemen, Ang Li, Henk Corporaal, Di Wu. 591-598 [doi]
- Hardware Design Space Exploration with a New Dimension - IP Protection RobustnessQiang Liu, Haie Li. 599-605 [doi]
- TEST: Assessing NoC Policies Facing Aging and Leakage PowerDavide Zoni, Luca Borghese, Giuseppe Massari, Simone Libutti, William Fornaciari. 606-613 [doi]
- SOC Power Management Strategy Based on Global Hardware Functional State AnalysisHend Affes, Michel Auguin. 614-620 [doi]
- An Analytic Approach on End-to-End Packet Error Rate Estimation for Network-on-ChipMichael Vonbun, Stefan Wallentowitz, Andreas Oeldemann, Andreas Herkersdorf. 621-628 [doi]
- Systematic Reverse Engineering of Cache Slice Selection in Intel ProcessorsGorka Irazoqui, Thomas Eisenbarth, Berk Sunar. 629-636 [doi]
- A System-Level Simulation Framework for Evaluating Resource Management Policies for Heterogeneous System ArchitecturesAntonio Miele, Gianluca Carlo Durelli, Marco Domenico Santambrogio, Cristiana Bolchini. 637-644 [doi]
- Suit up! - Made-to-Measure Hardware Implementations of ASCONHannes Groß, Erich Wenger, Christoph Dobraunig, Christoph Ehrenhofer. 645-652 [doi]
- Fast and Secure Finite Field MultipliersDanuta Pamula, Arnaud Tisserand. 653-660 [doi]
- A Petite and Power Saving Design for the AES S-BoxMarkus Stefan Wamser, Lukas Holzbaur, Georg Sigl. 661-667 [doi]
- New ASIC/FPGA Cost Estimates for SHA-1 CollisionsMuhammad Hassan, Ayesha Khalid, Anupam Chattopadhyay, Christian Rechberger, Tim Güneysu, Christof Paar. 669-676 [doi]
- IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing AnalysisIrune Agirre, Mikel Azkarate-askasua, Carles Hernandez, Jaume Abella, Jon Perez, Tullio Vardanega, Francisco J. Cazorla. 677-684 [doi]
- CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-CoresMilos Panic, Eduardo Quiñones, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 685-692 [doi]
- Time-Triggered Extension Layer for On-Chip Network Interfaces in Mixed-Criticality SystemsHamidreza Ahmadian, Roman Obermaisser. 693-699 [doi]
- Double Phase Fault Collapsing with Linear Complexity in Digital CircuitsRaimund Ubar, Lembit Jurimagi, Elmet Orasson, Galina Josifovska, Stephen Adeboye Oyeniran. 700-705 [doi]
- Matching Detection and Correction Schemes for Soft Error Handling in Sequential LogicErol Koser, Felix Miller, Walter Stechele. 706-713 [doi]
- A Detailed Characterization of Errors in Logic Circuits due to Single-Event TransientsNanditha P. Rao, Madhav P. Desai. 714-721 [doi]
- Enhanced Metastability Characterization Based on AC AnalysisThomas Polzer, Andreas Steininger. 722-729 [doi]
- DEWI - Wirelessly into the FutureWerner Rom, Peter Priller, Jani Koivusaari, Maarjana Komi, Ramiro Robles, Luis Dominguez, Javier Rivilla, Willem van Driel. 730-739 [doi]
- The Human Brain Project: High Performance Computing for Brain Cells Hw/Sw Simulation and UnderstandingEgidio D'Angelo, Giovanni Danese, Giordana Florimbi, Francesco Leporati, Alessandra Majani, Stefano Masoli, Sergio Solinas, Emanuele Torti. 740-747 [doi]
- Methodologies for the WCET Analysis of Parallel Applications on Many-Core ArchitecturesVincent Nélis, Patrick Meumeu Yomsi, Luís Miguel Pinho. 748-755 [doi]