Abstract is missing.
- A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGAArne Kreddig, Simon Conrady, Manu Manuel, Walter Stechele. 1-8 [doi]
- A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator DeploymentGianluca Bellocchi, Alessandro Capotondi, Francesco Conti 0001, Andrea Marongiu. 9-17 [doi]
- A Power-Efficient Parameter Quantization Technique for CNN AcceleratorsErcan Kalali, Rene van Leuken. 18-23 [doi]
- An efficient FPGA-based co-processor for feature point detection and trackingToms Sturmanis, Rihards Novickis. 24-29 [doi]
- Vector Processing Unit: A RISC-V based SIMD Co-processor for Embedded ProcessingMuhammad Ali 0010, Matthias von Ameln, Diana Goehringer. 30-34 [doi]
- An Open-Source Framework for the Generation of RISC-V Processor + CGRA Accelerator SystemsXiaoyi Ling, Takahiro Notsu, Jason Helge Anderson. 35-42 [doi]
- A Connected Component Labelling algorithm for a multi-pixel per clock cycle video streamMarcin Kowalczyk, Tomasz Kryjak. 43-50 [doi]
- An adaptive pixel accumulation algorithm for a 1D micro-scanning LiDARIevgeniia Maksymova, Christian Steger, Norbert Druml. 51-57 [doi]
- Managing the Resource Continuum in a Real Video Surveillance ScenarioFilippo Sciamanna, Michele Zanella, Giuseppe Massari, William Fornaciari. 58-61 [doi]
- A Boolean Heuristic for Disjoint SOP SynthesisPadmanabhan Balasubramanian, Anna Bernasconi 0001, Valentina Ciriani, Tiziano Villa. 62-68 [doi]
- Resynthesis of logic circuits using machine learning and reconvergent pathsJitka Kocnová, Zdenek Vasícek. 69-76 [doi]
- Decomposition of transition systems into sets of synchronizing state machinesViktor Teren, Jordi Cortadella, Tiziano Villa. 77-81 [doi]
- Efficient Implementation of Heterogeneous Dataflow Models using Synchronous IO PatternsOmair Rafique, Yu Bai 0003, Klaus Schneider 0001, Guangxi Yan. 82-89 [doi]
- Massively parallel binary neural network inference for detecting ships in FPGA systems on the edgeTadej Murovic, Andrej Trost. 90-96 [doi]
- Cache-accel: FPGA Accelerated Cache Simulator with Partially Reconfigurable PrefetcherShivani Shah, Vaibhavi Mathur, Sahithi Meenakshi Vutakuru, Kavya Borra, Nanditha P. Rao. 97-100 [doi]
- FPGA-based real-time monitoring support for CAN applicationsAlessandro Cilardo, Stefano Mercogliano. 101-106 [doi]
- Employing the Concept of Multilevel Security to Generate Access Protection Configurations for Automotive On-Board NetworksTobias Dörr, Timo Sandmann, Hannes Mohr, Jürgen Becker 0001. 107-114 [doi]
- Protecting IoT Devices through a Hardware-driven Memory VerificationTroya Çagil Köylü, Hans Okkerman, Cezar Rodolfo Wedig Reinbrecht, Said Hamdioui, Mottaqiallah Taouil. 115-122 [doi]
- Comparative Evaluation of Semi-Supervised Anomaly Detection Algorithms on High-Integrity Digital SystemsGianluca Martino, Arne Gruenhagen, Julien Branlard, Annika Eichler, Görschwin Fey, Holger Schlarb. 123-130 [doi]
- Fast Simulation of a Many-NPU Network-on-Chip for Microarchitectural Design Space ExplorationJintaek Kang, Changjae Yi, Keonjoo Lee, Seungwook Lee, Soojung Ryu, Soonhoi Ha. 131-138 [doi]
- Architectural Implementation of a Reconfigurable NoC Design for Multi-ApplicationsM. K. Aparna Nair, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi. 139-142 [doi]
- Network-on-ReRAM for Scalable Processing-in-Memory Architecture DesignBita Dabiri, Mehdi Modarressi, Masoud Daneshtalab. 143-149 [doi]
- Experimental Evaluation of Statistical Model Checking Methods for Probabilistic Timing Analysis of Multiprocessor SystemsHai-Dang Vu, Sebastien Le Nours, Sébastien Pillement. 150-157 [doi]
- Near-Data-Processing Architectures Performance Estimation and Ranking using Machine Learning PredictorsVeronia Iskandar, Mohamed A. Abd El ghany, Diana Goehringer. 158-165 [doi]
- Towards Machine Learning Support for Embedded System TestsStefan Scharoba, Kai-Uwe Basener, Jens Bielefeldt, Hans-Werner Wiesbrock, Michael Hübner 0001. 166-173 [doi]
- High Speed Implementation of the Deformable Shape Tracking Face Alignment AlgorithmNikos Petrellis, Stavros Zogas, Panagiotis Christakos, Georgios Keramidas, Panagiotis Mousouliotis, Nikolaos S. Voros, Christos P. Antonopoulos. 174-177 [doi]
- Highly Parallel Sample Rate Converter for Space Telemetry TransmittersMatteo Bertolucci, Luca Fanucci. 178-181 [doi]
- Single-Frame Direct Reflectance Estimation With Indirect Time-of-Flight CamerasCaterina Nahler, Armin Schoenlieb, Sebastian Handel, Hannes Plank, Christian Steger, Norbert Druml. 182-186 [doi]
- Evaluation of Time Series Clustering on Embedded Sensor PlatformWenyao Zhu, Zhonghai Lu. 187-191 [doi]
- An Investigation of Dynamic Partial Reconfiguration Offloading in Hard Real-Time SystemsGabriella D'Andrea, Giacomo Valente, Luigi Pomante, Tania Di Mascio. 192-198 [doi]
- A Hardware/Software Concept for Partial Logic Updates of Embedded Soft Processors at RuntimeTobias Scheipel, Peter Brungs, Marcel Baunach. 199-207 [doi]
- Metrics for the Evaluation of Approximate Sequential Streaming CircuitsSwantje Plambeck, Gianluca Martino, Görschwin Fey. 208-211 [doi]
- A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic EnvironmentsShayan Tabatabaei Nikkhah, Marc Geilen, Dip Goswami, Martijn Koedam, Andrew Nelson 0001, Kees Goossens. 212-220 [doi]
- ParalOS: A Scheduling & Memory Management Framework for Heterogeneous VPUsEvangelos Petrongonas, Vasileios Leon, George Lentaris, Dimitrios Soudris. 221-228 [doi]
- Scheduling Persistent and Fully Cooperative InstructionsYu Yang, Ahmed Hemani, Kolin Paul. 229-237 [doi]
- To Pin or Not to Pin: Asserting the Scalability of QEMU Parallel ImplementationMarie Badaroux, Saverio Miroddi, Frédéric Pétrot. 238-245 [doi]
- Gain and Pain of a Reliable Delay ModelJürgen Maier. 246-250 [doi]
- Heterogeneous Communication Virtualization for Distributed Embedded ApplicationsThinh Hung Pham, Shanker Shreejith, Sebastian Steinhorst, Suhaib A. Fahmy, Samarjit Chakraborty. 251-258 [doi]
- NMPO: Near-Memory Computing Profiling and OffloadingStefano Corda, Madhurya Kumaraswamy, Ahsan Javed Awan, Roel Jordans, Akash Kumar 0001, Henk Corporaal. 259-267 [doi]
- Programmable Systems for Intelligence in Automobiles (PRYSTINE): Final results after Year 3Norbert Druml, Anna Ryabokon, Rupert Schorn, Jochen Koszescha, Kaspars Ozols, Aleksandrs Levinskis, Rihards Novickis, Ethiopia Nigussie, Jouni Isoaho, Selim Solmaz, Georg Stettinger, Sergio Diaz, Mauricio Marcano, Jorge Villagra, Juan Medina, Martina Schwarz, Antonio Artuñedo, Mauro Comi, Rutger Beekelaar, Onur Özçelik, Elif Aksu Tasdelen, Yesim Gürbüz, Jan Saijets, Jukka Kyynäräinen, Dmitry Morits, Björn Debaillie, Maxim Rykunov, Joan Escamilla, Jarno Vanne, Tomi Korhonen, Kalle Holma, Eva-Maria Matzhold, Carlo Novara, Fabio Tango, Paolo Burgio, Giuseppe Calafiore, Milad Karimshoushtari, Emilie Boulay, Miguel Dhaens, Kylian Praet, Han Zwijnenberg, Henri Palm, David Aledo Ortega, Ercan Kalali, Tuomas Pensala, Arto Kyytinen, Morten Larsen, Omar Veledar, Georg Macher, Michael Lafer, Lorenzo Giraudi, Jakob Reckenzaun, Daniel Hammer, Naveen Mohan, Josef Schmid, Alfred Höß, Shai Ophir, Anand Dubey, Jonas Fuchs, Maximilian Lübke, Andrei Anghel, Nicolae-Catalin Ristea, Martin Törngren, Alua Musralina, Marlene Harter, Joseena Memadathil Jose, George Dimitrakopoulos. 268-277 [doi]
- Building Blocks and Interaction Patterns of Unmanned Aerial SystemsMahmoud Hussein, Réda Nouacer. 278-285 [doi]
- TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascaleGiovanni Agosta, Daniele Cattaneo 0002, William Fornaciari, Andrea Galimberti, Giuseppe Massari, Federico Reghenzani, Federico Terraneo, Davide Zoni, Carlo Brandolese, Massimo Celino, Francesco Iannone, Paolo Palazzari, Giuseppe Zummo, Massimo Bernaschi, Pasqua D'Ambra, Sergio Saponara, Marco Danelutto, Massimo Torquati, Marco Aldinucci, Yasir Arfat, Barbara Cantalupo, Iacopo Colonnelli, Roberto Esposito, Alberto Riccardo Martinelli, Gianluca Mittone, Olivier Beaumont, Bérenger Bramas, Lionel Eyraud-Dubois, Brice Goglin, Abdou Guermouche, Raymond Namyst, Samuel Thibault, Antonio Filgueras, Miquel Vidal, Carlos Álvarez 0001, Xavier Martorell, Ariel Oleksiak, Michal Kulczewski, Alessandro Lonardo, Piero Vicini, Francesca Lo Cicero, Francesco Simula, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Pier Stanislao Paolucci, Matteo Turisini, Francesco Giacomini, Tommaso Boccali, Simone Montangero, Roberto Ammendola. 286-294 [doi]
- Going to the Edge - Bringing Internet of Things and Artificial Intelligence TogetherMichael Karner, Joachim Hillebrand, Manuela Klocker, Ramiro Sámano-Robles. 295-302 [doi]
- AIDOaRt: AI-augmented Automation for DevOps, a Model-based Framework for Continuous Development in Cyber-Physical SystemsRomina Eramo, Vittoriano Muttillo, Luca Berardinelli, Hugo Brunelière, Abel Gómez, Alessandra Bagnato, Andrey Sadovykh, Antonio Cicchetti. 303-310 [doi]
- The H2020-ECSEL Project "iRel40" (Intelligent Reliability 4.0)Klaus Pressel, Josef Moser, Sven Rzepka, Klas Brinkfeldt, Susan Zhao, Willem D. van Driel, Paolo Giammatteo, Baris Bulut, Mujdat Soyturk, Luigi Pomante. 311-318 [doi]
- Pre-Integrated Architectures for sustainable complex Cyber-Physical SystemsP. Gougeon, Thierry Goubier, K. Nguyen, T. Arvieu. 319-324 [doi]
- RSM Protection of the PRESENT Lightweight Cipher as a RISC-V ExtensionEtienne Tehrani, Tarik Graba, Abdelmalek Si-Merabet, Jean-Luc Danger. 325-332 [doi]
- Secure and dependable: Area-efficient masked and fault-tolerant architecturesVojtech Miskovský, Hana Kubátová, Martin Novotný. 333-338 [doi]
- Studying OpenCL-based Number Theoretic Transform for heterogeneous platformsEvangelos Haleplidis, Thanasis Tsakoulis, Alexander El-Kady, Charis Dimopoulos, Odysseas G. Koufopavlou, Apostolos P. Fournaris. 339-346 [doi]
- Novel Non-cryptographic Hash Functions for Networking and Security Applications on FPGAThomas Claesen, Arish Sateesan, Jo Vliegen, Nele Mentens. 347-354 [doi]
- MaDMAN: Detection of Software Attacks Targeting Hardware VulnerabilitiesNikolaos Foivos Polychronou, Pierre-Henri Thevenon, Maxime Puys, Vincent Beroulle. 355-362 [doi]
- Analysis of a Laser-induced Instructions Replay Fault Model in a 32-bit MicrocontrollerVanthanh Khuat, Jean-Max Dutertre, Jean-Luc Danger. 363-370 [doi]
- Optical Fault Injection Attacks against Radiation-Hard Shift RegistersDmytro Petryk, Zoya Dyka, Roland Sorge, Jan Schäffner, Peter Langendörfer. 371-375 [doi]
- Towards a More Flexible IoT SAFE ImplementationDominic Pirker, Thomas Fischer, Christoph Reiter, Harald Witschnig, Christian Steger. 376-380 [doi]
- 5G Security: FPGA Implementation of SNOW-V Stream CipherLampros Pyrgas, Paris Kitsos. 381-384 [doi]
- Extending Circuit Design Flow for Early Assessment of Fault Attack VulnerabilitiesFelipe Valencia, Ilia Polian, Francesco Regazzoni 0001. 385-388 [doi]
- Checkpointing Period Optimization of Distributed Fail-Operational Automotive ApplicationsPhilipp Weiss, Emil Daporta, Andreas Weichslgartner, Sebastian Steinhorst. 389-395 [doi]
- *Jose A. Matute, Myriam Elizabeth Vaca Recalde, Joshué Pérez. 396-401 [doi]
- Controlled Intra-Platoon Collisions for Emergency Braking in Close-Distance Driving ArrangementsDharshan Krishna Murthy, Alejandro Masrur. 402-409 [doi]
- *Philipp Clément, Herbert Danzinger, Omar Veledar, Clemens Könczöl, Georg Macher, Arno Eichberger. 410-417 [doi]
- Runnable Configuration in Mixed Classic/Adaptive AUTOSAR Systems by Leveraging NondeterminismMilan Copic, Rainer Leupers, Gerd Ascheid. 418-425 [doi]
- Enabling Unit Testing of Already-Integrated AI Software Systems: The Case of Apollo for Autonomous DrivingMiguel Alcon, Hamid Tabani, Jaume Abella 0001, Francisco J. Cazorla. 426-433 [doi]
- TRe-Map: Towards Reducing the Overheads of Fault-Aware Retraining of Deep Neural Networks by Merging Fault MapsLe Ha Hoang, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 434-441 [doi]
- POMMEL: Exploring Off-Chip Memory Energy & Power Consumption in Convolutional Neural Network AcceleratorsAlexander Montgomerie-Corcoran, Christos-Savvas Bouganis. 442-448 [doi]
- Improving the Efficiency of Transformers for Resource-Constrained DevicesHamid Tabani, Ajay Balasubramaniam, Shabbir Marzban, Elahe Arani, Bahram Zonooz. 449-456 [doi]
- Co-designing Intelligent Control of Building HVACs and MicrogridsRumia Masburah, Sayan Sinha, Rajib Lochan Jana, Soumyajit Dey, Qi Zhu 0002. 457-464 [doi]
- Model-based System Architecture for Event-triggered Wireless Control of Bio-analytical DevicesKanwal Ashraf, Yannick Le Moullec, Tamás Pardy, Toomas Rang. 465-471 [doi]
- Modeling Battery SoC Predictions for Smart Connected Glasses SimulationsAlexis Arcaya-Jordan, Alain Pegatoquet, Andrea Castagnetti. 472-479 [doi]
- Oxygen Saturation Measurement using Hyperspectral Imaging targeting Real-Time MonitoringBeatriz Martinez-Vega, Raquel Leon, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó, David Suarez-Vega, Bernardino Clavo. 480-487 [doi]
- Design for Restricted-Area and Fast Dilution using Programmable Microfluidic Device based Lab-on-a-ChipShuaijie Ying, Sudip Roy 0001, Juinn-Dar Huang, Shigeru Yamashita. 488-494 [doi]
- Combining SWAPs and Remote CNOT Gates for Quantum Circuit TransformationPhilipp Niemann 0001, Luca Müller, Rolf Drechsler. 495-501 [doi]
- Towards Post-Quantum Enhanced Identity-Based EncryptionDariia Verchyk, Johanna Sepúlveda. 502-509 [doi]
- Digital Forensics, Video Forgery Recognition, for Cybersecurity SystemsIoannis Memos Bagkratsas, Nicolas Sklavos. 510-513 [doi]
- Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich NeuronLuíza C. Garaffa, Abdullah Aljuffri, Cezar Reinbrecht, Said Hamdioui, Mottaqiallah Taouil, Johanna Sepúlveda. 514-518 [doi]
- Automated Debugging-Aware Visualization Technique for SystemC HLS DesignsMehran Goli, Alireza Mahzoon, Rolf Drechsler. 519-526 [doi]
- Search Strategy of Large Nonlinear Block CodesOndrej Novák. 527-534 [doi]
- Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary TechniquesNikolaos I. Deligiannis, Riccardo Cantoro, Matteo Sonza Reorda. 535-540 [doi]
- An Automated Setup for Large-Scale Simulation-Based Fault-Injection Experiments on Asynchronous Digital CircuitsPatrick Behal, Florian Huemer, Robert Najvirt, Andreas Steininger. 541-548 [doi]
- Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAsJakub Lojda, Richard Panek, Zdenek Kotásek. 549-552 [doi]
- Reliability Analysis of the FPGA Control System with Reconfiguration HardeningRichard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek. 553-556 [doi]
- Implementation-Independent Test Generation for a Large Class of Faults in RISC Processor ModulesMaksim Jenihhin, Adeboye Stephen Oyeniran, Jaan Raik, Raimund Ubar. 557-561 [doi]