Abstract is missing.
- Building a Better Random Number Generator for Stochastic ComputingFlorian Neugebauer, Ilia Polian, John P. Hayes. 1-8 [doi]
- Rapid Estimation of Power-Management Unit Overhead from System-Level SpecificationDominik Macko. 9-13 [doi]
- Loop Overhead Reduction Techniques for Coarse Grained Reconfigurable ArchitecturesKanishkan Vadivel, Mark Wijtvliet, Roel Jordans, Henk Corporaal. 14-21 [doi]
- Autonomous Power Management for Embedded Systems Using a Non-linear Power PredictorSidartha A. L. Carvalho, Daniel C. Cunha, Abel Guilhermino da Silva Filho. 22-29 [doi]
- An Aspect and Transaction Oriented Programming, Design and Verification Language (PDVL)Tobias Strauch. 30-39 [doi]
- Optimizing Memory Access Performance Using Hardware Assisted Virtualization in Retargetable Dynamic Binary TranslationAntoine Faravelon, Olivier Gruber, Frédéric Pétrot. 40-46 [doi]
- Static Write Buffer Cache Modeling to Increase Host-Compiled Simulation AccuracyHector Posadas, Luis Diaz, Eugenio Villar. 47-53 [doi]
- Assertion-Based Verification for SoC Models and Identification of Key EventsLaurence Pierre, Martial Chabot. 54-61 [doi]
- An Architecture for Online-Diagnosis Systems Supporting Compressed CommunicationSeungbum Jo, Markus Lohrey, Damian Ludwig, Simon Meckel, Roman Obermaisser, Simon Plasger. 62-69 [doi]
- A Hardware/Software Codesign for the Chemical Reactivity of BRAMSCarlos Alberto Oliveira De Souza, Erinaldo Pereira, Eduardo Marques. 70-77 [doi]
- Nepteron Processor for Real-Time Computation of Conductance-Based Neuronal NetworksMarcel Beuler, Alexander Krum, Werner Bonath, Hartmut Hillmer. 78-85 [doi]
- System-Aware Performance Monitoring Unit for RISC-V ArchitecturesTobias Scheipel, Fabian Mauroner, Marcel Baunach. 86-93 [doi]
- SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUsSyed Mohammad Asad Hassan Jafri, Ahmed Hemani, Leonardo Intesa. 94-101 [doi]
- EventIRQ: An Event Based and Priority Aware IRQ Handling for Multi-tasking EnvironmentsFabian Mauroner, Marcel Baunach. 102-110 [doi]
- Design of an On-chip System for the SET Pulse Width MeasurementMarko S. Andjelkovic, Vladimir Petrovic, Miljana Nenadovic, Anselm Breitenreiter, Milos Krstic, Rolf Kraemer. 111-118 [doi]
- Acceleration Techniques for System-Hyper-Pipelined Soft-Processors on FPGAsTobias Strauch. 119-128 [doi]
- Application Specific Behavioral Synthesis Design Space Exploration: Artificial Neural Networks. A Case StudyBenjamin Carrión Schäfer, David Aledo, Félix Moreno. 129-136 [doi]
- Composition of Switching Lattices and Autosymmetric Boolean Function SynthesisAnna Bernasconi 0001, Valentina Ciriani, Luca Frontini, Gabriella Trucco. 137-144 [doi]
- Performance Targeted Minimization of Incompletely Specified Finite State Machines for Implementation in FPGA DevicesAdam Klimowicz. 145-150 [doi]
- A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA ToolchainsAlessandro Pappalardo, Giuseppe Natale, Marco Domenico Santambrogio. 151-154 [doi]
- Analysis and Visualization of Product Memory Layout in IP-XACTEsko Pekkarinen, Mikko Teuho, Timo Hämäläinen. 155-162 [doi]
- SAT-Based Generation of Optimum Function Implementations with XOR GatesPetr Fiser, Ivo Halecek, Jan Schmidt. 163-170 [doi]
- Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer SharingCharles Effiong, Gilles Sassatelli, Abdoulaye Gamatié. 171-178 [doi]
- Packet Classification with Limited Memory ResourcesMichal Kekely, Jan Korenek. 179-183 [doi]
- A Distributed NUCA Architecture Using an Efficient NoC Multicasting SupportHela Belhadj Amor, Abbas Sheibanyrad, Frédéric Pétrot. 184-191 [doi]
- A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore SystemsYves Durand, Christian Bernard, Romain Lemaire, César Fuguet Tortolero, Emilie Garat. 192-197 [doi]
- Automatic Control Flow Generation for OpenVX GraphsMerten Popp, Stef van Son, Orlando Moreira. 198-204 [doi]
- Higher-Order Side-Channel Protected Implementations of KECCAKHannes Groß, David Schaffenrath, Stefan Mangard. 205-212 [doi]
- Lightweight Software Encryption for Embedded ProcessorsThomas Hiscock, Olivier Savry, Louis Goubin. 213-220 [doi]
- A Design Strategy for Digit Serial Multiplier Based Binary Edwards Curve Scalar Multiplier ArchitecturesApostolos P. Fournaris, Charalambos Dimopoulos, Odysseas G. Koufopavlou. 221-228 [doi]
- Hardware-Secured Configuration and Two-Layer Attestation Architecture for Smart SensorsThomas Ulz, Thomas W. Pieber, Christian Steger, Sarah Haas, Rainer Matischek, Holger Bock. 229-236 [doi]
- Side Channel Evaluation of PUF-Based Pseudorandom PermutationDurga Prasad Sahoo, Phuong Ha Nguyen, Debapriya Basu Roy, Debdeep Mukhopadhyay, Rajat Subhra Chakraborty. 237-243 [doi]
- How Microprobing Can Attack Encrypted MemorySergei Skorobogatov. 244-251 [doi]
- Role of Laser-Induced IR Drops in the Occurrence of Faults: Assessment and SimulationRaphael Andreoni Camponogara Viera, Jean-Max Dutertre, Rodrigo Possamai Bastos, Philippe Maurine. 252-259 [doi]
- Influence of Fault-Tolerance Techniques on Power-Analysis Resistance of Cryptographic DesignJan Riha, Vojtech Miskovský, Hana Kubátová, Martin Novotný. 260-267 [doi]
- Thermal Sensor Based Hardware Trojan Detection in FPGAsLampros Pyrgas, Filippos Pirpilidis, Aliki Panayiotarou, Paris Kitsos. 268-273 [doi]
- Analysis and Inner-Round Pipelined Implementation of Selected Parallelizable CAESAR Competition CandidatesSanjay Deshpande, Kris Gaj. 274-282 [doi]
- Counterfeit IC Detection By Image Texture AnalysisPallabi Ghosh, Rajat Subhra Chakraborty. 283-286 [doi]
- Run-Time Effect by Inserting Hardware Trojans, in Combinational CircuitsFotios Kounelis, Nicolas Sklavos, Paris Kitsos. 287-290 [doi]
- Exploiting Quantum Gates in Secure ComputationMaryam Ehsanpour, Stelvio Cimato, Valentina Ciriani, Ernesto Damiani. 291-294 [doi]
- IoT Components LifeCycle Based Security AnalysisJohan Marconot, Florian Pebay-Peyroula, David Hély. 295-298 [doi]
- Necessity of Fault Tolerance Techniques in Xilinx Kintex 7 FPGA Devices for Space Missions: A Case StudyLouis van Harten, Roel Jordans, Hamid Reza Pourshaghaghi. 299-306 [doi]
- SAT-Based ATPG for Zero-Aliasing CompactionRobert Hulle, Petr Fiser, Jan Schmidt. 307-314 [doi]
- A Functional Test Framework to Observe MPSoC Power Management Techniques in Virtual PlatformsSören Schreiner, Maher Fakih, Kim Grüttner, Duncan Graham, Wolfgang Nebel, Salvador Peiro Frasquet. 315-322 [doi]
- PCG: Partially Clock-Gating Approach to Reduce the Power Consumption of Fault-Tolerant Register FilesAlireza Namazi, Meisam Abdollahi. 323-328 [doi]
- Setup for an Experimental Study of Radiation Effects in 65nm CMOSBernhard Fritz, Andreas Steininger, Vaclav Simek, Varadan Savulimedu Veeravalli. 329-336 [doi]
- Reliability Analysis and Improvement of FPGA-Based Robot ControllerJakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek. 337-344 [doi]
- Thermal Effect on Performance, Power, and BTI Aging in FinFET-Based DesignsWarin Sootkaneung, Suppachai Howimanporn, Sasithorn Chookaew. 345-351 [doi]
- On Dependability Assessment of Fault Tolerant Systems by Means of Statistical Model CheckingJosef Strnadel. 352-355 [doi]
- A Probabilistic Context-Free Grammar Based Random Test Program GenerationOndrej Cekan, Zdenek Kotásek. 356-359 [doi]
- Dependability Prediction Involving Temporal Redundancy and the Effect of Transient FaultsMartin Danhel, Filip Stepánek, Hana Kubátová. 360-363 [doi]
- LORAP: Low-Overhead Power and Reliability-Aware Task Mapping Based on Instruction Footprint for Real-Time ApplicationsAlireza Namazi, Meisam Abdollahi, Saeed Safari, Siamak Mohammadi. 364-367 [doi]
- A 3D Time-of-Flight Mixed-Criticality System for Environment PerceptionJosef Steinbaeck, Allan Tengg, Gerald Holweg, Norbert Druml. 368-374 [doi]
- A Subplatooning Strategy for Safe Braking ManeuversDharshan Krishna Murthy, Alejandro Masrur. 375-382 [doi]
- On the Benefits of Multicores for Real-Time SystemsSelma Saidi. 383-389 [doi]
- FPGA-Centric High Performance Embedded Computing: Challenges and TrendsRabie Ben Atitallah, Karim M. A. Ali. 390-395 [doi]
- A Survey on Open-Source Flight Control Platforms of Unmanned Aerial VehicleEmad Ebeid, Martin Skriver, Jie Jin. 396-402 [doi]
- A Scalable Cloud Computing Infrastructure for Geospatial Data Analytics for Change DetectionRune Hylsberg Jacobsen, Jacob Hoxbroe Jeppesen, Kim Fibiger Laursen, John Skovsgaard, Henrik Nymann Jensen, Thomas Skjødeberg Toftegaard. 403-410 [doi]
- Evaluating the Impact of Communication Network Performance on Supervisory Supermarket ControlJacob Theilgaard Madsen, Tomasz Minko, Tatiana K. Madsen, Hans-Peter Schwefel. 411-418 [doi]
- Modular Development and Certification of Dependable Mixed-Criticality SystemsAsier Larrucea, Imanol Martinez, Carlos Fernando Nicolas, Jon Perer, Roman Obermaisser. 419-426 [doi]
- Mixed Time-Criticality Process Interferences Characterization on a Multicore Linux SystemFederico Reghenzani, Giuseppe Massari, William Fornaciari. 427-434 [doi]
- Model-Based Function Mapping and Bandwidth Reservation for Mixed-Critical Adaptive SystemsMahmoud Hussein, Ansgar Radermacher, Réda Nouacer. 435-439 [doi]
- Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing AnalysisMladen Slijepcevic, Carles Hernández, Jaume Abella, Francisco J. Cazorla. 440-444 [doi]
- The HELICoiD Project: Parallel SVM for Brain Cancer ClassificationEmanuele Torti, Camilla Cividini, Alessandro Gatti, Giovanni Danese, Francesco Leporati, Himar Fabelo, Samuel Ortega, Gustavo Marrero Callicó. 445-450 [doi]
- Hardware Platforms Benchmark For Real-Time Polyp DetectionQuentin Angermann, Aymeric Histace, Maroua Hammami, Mehdi Terosiet, Lionel Faurlini, Olivier Romain. 451-455 [doi]
- Wireless and Portable System for the Study of in-vitro Cell Culture Impedance Spectrum by Electrical Impedance SpectroscopyEdwin De Roux, Mehdi Terosiet, F. Kolbl, J. Chrun, P. H. Aubert, P. Banet, M. Boissiere, E. Pauthe, Aymeric Histace, Olivier Romain. 456-461 [doi]
- Towards a Mobile Health Platform with Parallel Processing and Multi-sensor CapabilitiesFlorian Glaser, Philipp Schönle, Pascale Meier, Jonathan Bosser, Noé Brun, Thomas Burger, Schekeb Fateh, Giovanni Rovere, Luca Benini, Qiuting Huang. 462-469 [doi]
- Towards a Safe Software Development EnvironmentMahmoud Hussein, Réda Nouacer, Ansgar Radermacher. 470-477 [doi]
- MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC SystemsJose Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, Jose Maria Martinez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomas Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni. 478-485 [doi]
- Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution: The ExaNoDe ApproachAlvise Rigo, Christian Pinto, Kevin Pouget, Daniel Raho, Denis Dutoit, Pierre-Yves Martinez, Chris Doran, Luca Benini, Iakovos Mavroidis, Manolis Marazakis, Valeria Bartsch, Guy Lonsdale, Antoniu Pop, John Goodacre, Annaik Colliot, Paul M. Carpenter, Petar Radojkovic, Dirk Pleiter, Dominique Drouin, Benoît Dupont de Dinechin. 486-493 [doi]
- The MegaM@Rt2 ECSEL Project: MegaModelling at Runtime - Scalable Model-Based Framework for Continuous Development and Runtime Validation of Complex SystemsWasif Afzal, Hugo Brunelière, Davide Di Ruscio, Andrey Sadovykh, Silvia Mazzini, Eric Cariou, Dragos Truscan, Jordi Cabot, Daniel Field, Luigi Pomante, Pavel Smrz. 494-501 [doi]
- Security & Trusted Devices in the Context of Internet of Things (IoT)Nicolas Sklavos, Ioannis D. Zaharakis, Achilles Kameas, Angeliki Kalapodi. 502-509 [doi]
- The Next Generation of Exascale-Class Systems: The ExaNeSt ProjectRoberto Ammendola, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Piero Vicini, Giuliano Taffoni, Jose A. Pascual, Javier Navaridas, Mikel Luján, John Goodacre, Nikolaos Chrysos, Manolis Katevenis. 510-515 [doi]
- Exploiting Kant and Kimura's Matrix Inversion Algorithm on FPGAAndré B. Perina, Paulo Matias, Eduardo Marques, Vanderlei Bonato, João Miguel Gago Pontes de Brito Lima. 516-519 [doi]
- Designing a Synthetic Aperture Radar's Data Formatting and Antenna Gyro Stabilizing ModuleRicardo de Porras Bernacer. 520-523 [doi]
- Two-Phase Interarrival Time Prediction for Runtime Resource ManagementMina Niknafs, Ivan Ukhov, Petru Eles, Zebo Peng. 524-528 [doi]
- Low-Cost Sub-5W Processors for Edge HPCPedro Trancoso, Michalis Efstathiou. 529-532 [doi]
- A Methodology for Predicting Application-Specific Achievable Memory Bandwidth for HW/SW-CodesignMatthias Göbel, Ahmed Elhossini, Ben H. H. Juurlink. 533-537 [doi]
- Adaptive Reliability for Fault Tolerant Multicore SystemsIhsen Alouani, Thomas Wild, Andreas Herkersdorf, Smaïl Niar. 538-542 [doi]
- High-Performance General-Purpose Arithmetic Operations Using the Massive Parallel DNA-Based ComputationMercedeh Sanjabi, Ali Jahanian, Maryam Tahmasebi. 543-546 [doi]
- Optimal Placement of Heterogeneous Uncore Component in 3D Chip-MultiprocessorsAniseh Dorostkar, Arghavan Asad, Mahmood Fathy, Farah Mohammadi. 547-551 [doi]