Table of Contents

• SiP design flow and 3D DRC for MEMSA. Mehdaoui, J. Pagazani, G. Schropfer, G. Lissorgues. 12-13 [doi]
• Development of 3D space partitioning and design rule check for smart system solutionsStefano Pettazzi, Andrew Plews, Anatoly Rudenko, Ahmed Nejim. 14 [doi]
• Studying DAC capacitor-array degradation in charge-redistribution SAR ADCsM. A. Khan, H. G. Kerkhoff. 15-20 [doi]
• Automatically connecting hardware blocks via light-weight matching techniquesJan Malburg, N. Krafczyk, Görschwin Fey. 21-26 [doi]
• A double-path intra prediction architecture for the hardware H.265/HEVC encoderAndrzej Abramowski, Grzegorz Pastuszak. 27-32 [doi]
• Online test vector insertion: A concurrent built-in self-testing (CBIST) approach for asynchronous logicJ. Maier, Andreas Steininger. 33-38 [doi]
• Quality assurance in memory built-in self-test toolsAlbert Au, Artur Pogiel, Janusz Rajski, Piotr Sydow, Jerzy Tyszer, Justyna Zawada. 39-44 [doi]
• Generic built-in self-repair architectures for SoC logic coresMarcel Baláz, Stefan Kristofik, Mária Fischerová. 45-50 [doi]
• A 64-MHz∼640-MHz 64-phase clock generatorHong-Yi Huang, Jen-Chieh Liu, Shi-Jia Sun, Cheng-Hao Fu, Kuo-Hsing Cheng. 51-54 [doi]
• A design of an area-efficient 10-GHz phase-locked loop for source-synchronous, multi-channel links in 90-nm CMOS technologyWoo-Rham Bae, Deog Kyoon Jeong, Byoung-Joo Yoo. 55-58 [doi]
• Burst-pulse Generator based on transmission line toward sub-MMWParit Kanjanavirojkul, Nguyen Ngoc Mai Khanh, Toru Nakura, Kunihiro Asada. 59-64 [doi]
• A 120V high voltage DAC array for a tunable antenna in communication systemJing Ning, Klaus Hofmann. 65-70 [doi]
• Fast time-parallel C-based event-driven RTL simulationTariq Bashir Ahmad, Maciej J. Ciesielski. 71-76 [doi]
• Lower bounds of the size of Shared Structurally Synthesized BDDsRaimund Ubar, Dmitri Mironov. 77-82 [doi]
• BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result cachingRoel Jordans, Erkan Diken, Lech Józwiak, Henk Corporaal. 83-88 [doi]
• Analysis of current conveyor non-idealities for implementation as integrator in delta sigma modulatorsHarish Balasubramaniam, Klaus Hofmann. 89-92 [doi]
• Multistage low ripple charge pumpAndrzej Grodzicki, Witold A. Pleskacz. 93-98 [doi]
• A novel impedance calculation method and its time efficiency evaluationJuraj Brenkus, Viera Stopjaková, Daniel Arbet, Gábor Gyepes, Libor Majer. 99-103 [doi]
• Test-data compression with low number of channels and short test timeOndrej Novák, Jiri Jenícek, Martin Rozkovec. 104-109 [doi]
• Test data compression based on reuse and bit-flipping of parts of dictionary entriesPanagiotis Sismanoglou, Dimitris Nikolos. 110-115 [doi]
• Timing-aware ATPG for critical paths with multiple TSVsCarolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. 116-121 [doi]
• A layout based customized testing technique for total microfluidic operations in digital microfluidic biochipsPranab Roy, Hafizur Rahaman, Parthasarathi Dasgupta. 122-128 [doi]
• Optimizing DD-based synthesis of reversible circuits using negative control linesEleonora Schönborn, Kamalika Datta, Robert Wille, Indranil Sengupta, Hafizur Rahaman, Rolf Drechsler. 129-134 [doi]
• Evolutionary design of approximate multipliers under different error metricsZdenek Vasícek, Lukás Sekanina. 135-140 [doi]
• Online testing of many-core systems in the Dark Silicon eraMohammad Hashem Haghbayan, Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 141-146 [doi]
• Reliable execution of statechart-generated correct embedded software under soft errorsRonaldo Rodrigues Ferreira, Thomas Klotz, Thilo Vörtler, Jean da Rolt, Gabriel L. Nazar, Álvaro Freitas Moreira, Luigi Carro, Karsten Einwich. 147-152 [doi]
• Combining fault tolerance and self repair at minimum cost in power and hardwareTobias Koal, Mario Schölzel, Heinrich Theodor Vierhaus. 153-158 [doi]
• Self-managing power management unitDominik Macko, Katarina Jelemenska. 159-162 [doi]
• A low supply voltage synchronous mirror delay with quadrature phase outputYo-Hao Tu, Kuo-Hsing Cheng, Chih-Hsun Hsu, Hong-Yi Huang. 163-166 [doi]
• High throughput architecture for the Advanced Encryption Standard AlgorithmSalma Hesham, Mohamed A. Abd El ghany, Klaus Hofmann. 167-170 [doi]
• Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGALukas Miculka, Zdenek Kotásek. 171-174 [doi]
• Low latency book handling in FPGA for high frequency tradingMilan Dvorak, Jan Korenek. 175-178 [doi]
• CRC based hashing in FPGA using DSP blocksTomás Závodník, Lukas Kekely, Viktor Pus. 179-182 [doi]
• The LSI implementation of a memory based field programmable device for MCU peripheralsTetsuya Matsumura, Naoya Okada, Yoshifumi Kawamura, Koji Nii, Kazutami Arimoto, Hiroshi Makino, Yoshio Matsuda. 183-188 [doi]
• Design methodology of configurable high performance packet parser for FPGAViktor Pus, Lukas Kekely, Jan Korenek. 189-194 [doi]
• A study on fast pipelined pseudo-random number generator based on chaotic logistic mapPawel Dabal, Ryszard Pelka. 195-200 [doi]
• Modeling timing constraints for automatic generation of embedded test instrumentsSteffen Ostendorff, Jorge H. Meza Escobar, Heinz-Dietrich Wuttke, T. Sasse, S. Richter. 201-206 [doi]
• Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounceAnu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. 207-212 [doi]
• Test and diagnosis of power switchesMiroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot. 213-218 [doi]
• Fast lookup for dynamic packet filtering in FPGALukas Kekely, Martin Zádník, Jirí Matousek, Jan Korenek. 219-222 [doi]
• Protecting combinational logic in pipelined microprocessor cores against transient and permanent faultsI. Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri. 223-225 [doi]
• Stabilization methods for integrated high voltage charge pumpsLufei Shen, Ferdinand Keil, Klaus Hofmann. 226-229 [doi]
• FPGA design of the computation unit for the semi-global stereo matching algorithmMikolaj Roszkowski, Grzegorz Pastuszak. 230-233 [doi]
• System design for enhanced forward-engineering possibilities of safety critical embedded systemsMartin Krammer, Michael Karner, Anton Fuchs. 234-237 [doi]
• Mismatch effects and their correction in large area ASICsPiotr Maj. 238-241 [doi]
• A unified CMOS inverter model for planar and FinFET nanoscale technologiesPanagiotis Chaourani, Spyridon Nikolaidis. 242-245 [doi]
• A new architecture for minimum mean square error sorted QR decomposition for MIMO wireless communication systemsVictor Tomashevich, Christina Gimmler-Dumont, Christian Fesl, Norbert Wehn, Ilia Polian. 246-249 [doi]
• Dedicated hardware architecture for object tracking preprocessing implemented in FPGAPeter Malík. 250-253 [doi]
• Emulation based fault injection on UHF RFID transponderOmar Abdelmalek, David Hély, Vincent Beroulle. 254-257 [doi]
• Sources of bias in EDA tools and its influencePetr Fiser, Jan Schmidt, Jiri Balcarek. 258-261 [doi]
• Automatic and reliable electrical characterization of MOSFETsZ. Stamenkovic, N. D. Vasovic, G. S. Ristic. 262-265 [doi]
• An approach towards selection of the oscillation frequency for oscillation test of analog ICsMartin Kovác, Daniel Arbet, Gabriel Nagy, Viera Stopjaková. 266-267 [doi]
• Customer return detection with features selectionDomenico Bertoncelli, Pasquale Caianiello. 268-269 [doi]
• Designing of Test Pattern Generators for stimulation of crosstalk faults in bus-type connectionsTomasz Garbolino. 270-273 [doi]
• On NFA-split architecture optimizationsVlastimil Kosar, Jan Korenek. 274-277 [doi]
• ADCs in deep submicron technologies for ASICs of pixel architecturePiotr Otfinowski, Pawel Grybos, Robert Szczygiel, Piotr Maj. 278-281 [doi]
• Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuitsKevin Ngari Muriithi, Toru Nakura, Kunihiro Asada. 282-285 [doi]
• On the in-field test of Branch Prediction Units using the correlated predictor mechanismMarco Gaudesi, S. Saleem, E. Sanchez, Matteo Sonza Reorda, E. Tanowe. 286-289 [doi]
• FPGA architectures of the quantization and the dequantization for video encodersGrzegorz Pastuszak. 290-293 [doi]
• An efficient hardware architecture for inter-prediction in H.264/AVC encodersNam-Khanh Dang, Xuan-Tu Tran, Alain Merirot. 294-297 [doi]
• An intra-cell defect grading toolAlberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi. 298-301 [doi]
• Heuristic algorithm of two-level minimization of fuzzy logic functionsAndrzej Wielgus. 302-305 [doi]
• Verifying robust frequency domain properties of non linear oscillators using SMTHafiz ul Asad, Kevin D. Jones, Frederic Surre. 306-309 [doi]
• Modeling and analysis of cracked through silicon via (TSV) interconnectionsVasileios Gerakis, Christina Avdikou, Alexandros Liolios, Alkis A. Hatzopoulos. 310-313 [doi]
• Case study: BISR for a processor multiplierAndrej Kincel, Marcel Baláz. 314-317 [doi]
• Efficient VHDL implementation of symbol synchronization for software radio based on FPGAPavel Fiala, Richard Linhart. 318-321 [doi]