An efficient hardware architecture for inter-prediction in H.264/AVC encoders

Nam-Khanh Dang, Xuan-Tu Tran, Alain Merirot. An efficient hardware architecture for inter-prediction in H.264/AVC encoders. In 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014. pages 294-297, IEEE, 2014. [doi]

Abstract

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