Table of Contents

• RBSA: Range-based simulated annealing for FPGA placementJunqi Yuan, Lingli Wang, Xuegong Zhou, Yinshui Xia, Jianping Hu. 1-8 [doi]
• Automatic circuit design and modelling for heterogeneous FPGAsSadegh Yazdanshenas, Vaughn Betz. 9-16 [doi]
• Liquid: High quality scalable placement for large heterogeneous FPGAsDries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt. 17-24 [doi]
• Performance characterization of Altera and Xilinx 28 nm FPGAs at cryogenic temperaturesHarald Homulle, Edoardo Charbon. 25-31 [doi]
• High performance serial ATA Gen3 controllers on FPGA devicesDan Cristian Turicu, Octavian Cret, Lucia Vacariu. 32-39 [doi]
• SMEFF: A scalable memory extension fabric for FPGAWei Li, Yangyang Zhao, Yuhang Liu, Mingyu Chen. 40-47 [doi]
• AXI over Ethernet; a protocol for the monitoring and control of FPGA clustersWilliam Kamp. 48-55 [doi]
• Ultra-low latency continuous block-parallel stream windowing using FPGA on-chip memoryJustin S. J. Wong, Runbin Shi, Maolin Wang, Hayden Kwok-Hay So. 56-63 [doi]
• HopliteRT: An efficient FPGA NoC for real-time applicationsSaud Wasly, Rodolfo Pellizzoni, Nachiket Kapre. 64-71 [doi]
• architect: Arbitrary-precision constant-hardware iterative computeHe Li, James J. Davis, John Wickerson, George A. Constantinides. 73-79 [doi]
• A state machine block for high-level synthesisShadi Assadikhomami, Jennifer Ongko, Tor M. Aamodt. 80-87 [doi]
• An IP core integration tool-flow for prototyping software-defined radios using static dataflow with access patternsLekhobola J. Tsoeunyane, Simon Winberg, Michael Inggs. 88-95 [doi]
• Synthesis of program binaries into FPGA accelerators with runtime dependence validationShaoyi Cheng, Qijing Huang, John Wawrzynek. 96-103 [doi]
• Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAsFelix Winterstein, George A. Constantinides. 104-111 [doi]
• Single window stream aggregation using reconfigurable hardwarePrajith Ramakrishnan Geethakumari, Vincenzo Gulisano, Bo Joel Svensson, Pedro Trancoso, Ioannis Sourdis. 112-119 [doi]
• Toward a new HLS-based methodology for FPGA benchmarking of candidates in cryptographic competitions: The CAESAR contest case studyEkawat Homsirikamol, Kris Gaj. 120-127 [doi]
• Comparing the cost of protecting selected lightweight block ciphers against differential power analysis in low-cost FPGAsWilliam Diehl, Abubakr Abdulgadir, Jens-Peter Kaps, Kris Gaj. 128-135 [doi]
• Accelerating NFV application using CPU-FPGA tightly coupled architectureYoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura. 136-143 [doi]
• An energy efficient approach for C4.5 algorithm using OpenCL design flowHai Peng, Xiaofan Zhang, Letian Huang. 144-151 [doi]
• Exploring automated space/time tradeoffs for OpenVX compute graphsHossein Omidian, Guy G. F. Lemieux. 152-159 [doi]
• NnCore: A parameterized non-linear function generator for machine learning applications in FPGAsSam M. H. Ho, Hayden Kwok-Hay So. 160-167 [doi]
• An object detector based on multiscale sliding window search using a fully pipelined binarized CNN on an FPGAHiroki Nakahara, Haruyoshi Yonekawa, Shimpei Sato. 168-175 [doi]
• Lowering dynamic power in stream-based harris corner detection architectureSiew Kei Lam, Rakesh Kumar Bijarniya, Meiqing Wu. 176-182 [doi]
• A 42fps full-HD ORB feature extraction accelerator with reduced memory overheadRongdi Sun, Peilin Liu, Jun Wang, Cecil Accetti, Abid A. Naqvi. 183-190 [doi]
• A scalable hybrid architecture for high performance data-parallel applicationsMoucheng Yang, Jifang Jin, Zhehao Li, Xuegong Zhou, Shaojun Wang, Lingli Wang. 191-194 [doi]
• Homeostatic fault tolerance in spiking neural networks utilizing dynamic partial reconfiguration of FPGAsAnju P. Johnson, Junxiu Liu, Alan G. Millard, Shvan Karim, Andy M. Tyrrell, Jim Harkin, Jon Timmis, Liam McDaid, David M. Halliday. 195-198 [doi]
• Model-based hardware design based on compatible sets of isomorphic subgraphsPatrick Sittel, Konrad Möller, Martin Kumm, Peter Zipf, Bogdan Pasca, Mark Jervis. 199-202 [doi]
• A NoC-based custom FPGA configuration memory architecture for ultra-fast micro-reconfigurationAmit Kulkarni 0002, Poona Bahrebar, Dirk Stroobandt, Giulio Stramondo, Catalin Bogdan Ciobanu, Ana Lucia Varbanescu. 203-206 [doi]
• An FPGA-based processor for training convolutional neural networksZhiqiang Liu, Yong Dou, Jingfei Jiang, Qiang Wang 0006, Paul Chow. 207-210 [doi]
• An FPGA-accelerated high-throughput data optimization system for high-speed transfer via wide area networkKentaro Katayama, Hidetoshi Matsumura, Hiroaki Kameyama, Shinichi Sazawa, Yasuhiro Watanabe. 211-214 [doi]
• Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processorNam Ho, Paul Kaufmann, Marco Platzner. 215-218 [doi]
• An open source PXIe ecosystem based on FPGA modulesAndrew Ang, Matt Bourne, Robin Dykstra. 219-222 [doi]
• FPGA-based high-performance time-to-digital converters by utilizing multi-channels looped carry chainsKe Cui, Zongkai Liu, Rihong Zhu, Xiangyu Li. 223-226 [doi]
• Instruction driven cross-layer CNN accelerator with winograd transformation on FPGAJincheng Yu, Yiming Hu, Xuefei Ning, Jiantao Qiu, Kaiyuan Guo, Yu Wang 0002, Huazhong Yang. 227-230 [doi]
• An FPGA-based tree crown detection approach for remote sensing imagesWeijia Li, Conghui He, Haohuan Fu, Wayne Luk. 231-234 [doi]
• A light-weight hardware/software co-design for pairing-based cryptography with low power and energy consumptionAhmad Salman, William Diehl, Jens-Peter Kaps. 235-238 [doi]
• FPGA-based training of convolutional neural networks with a reduced precision floating-point libraryRoberto DiCecco, Lin Sun, Paul Chow. 239-242 [doi]
• Selection of an error-correcting code for FPGA-based physical unclonable functionsBrian Jarvis, Kris Gaj. 243-246 [doi]
• Streaming sorting network based BWT acceleration on FPGA for lossless compressionBaofu Zhao, Yubin Li, Yu Wang, Huazhong Yang. 247-250 [doi]
• Runtime rule-reconfigurable high throughput NIPS on FPGAP. M. K. Tharaka, D. M. D. Wijerathne, Navoda Perera, Dinushan Vishwajith, Ajith Pasqual. 251-254 [doi]
• Designing and accelerating spiking neural networks using OpenCL for FPGAsArtur Podobas, Satoshi Matsuoka. 255-258 [doi]
• Customizable FPGA OpenCL matrix multiply design template for deep neural networksJack Yinger, Eriko Nurvitadhi, Davor Capalija, Andrew C. Ling, Debbie Marr, Krishnan Srivatsan, Duncan J. M. Moss, Suchit Subhaschandra. 259-262 [doi]
• A comprehensive hardware/software infrastructure for IP cores design protectionBrice Colombier, Lilian Bossuet, Ugo Mureddu, David Hély. 263-266 [doi]
• hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled cloudsQian Zhao 0001, Hendarmawan, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 267-270 [doi]
• Calling hardware procedures in a reconfigurable accelerator using RPC-FPGAErik H. D'Hollander, Bruno Chevalier, Koen De Bosschere. 271-274 [doi]
• FPGA-based ORB feature extraction for real-time visual SLAMWeikang Fang, Yanjun Zhang, Bo Yu, Shaoshan Liu. 275-278 [doi]
• PipeCNN: An OpenCL-based open-source FPGA accelerator for convolution neural networksDong Wang, Ke Xu, Diankun Jiang. 279-282 [doi]
• Hough transform line reconstruction on FPGA using back-projectionDonald G. Bailey. 283-286 [doi]
• FPGA implementation of convolutional neural network based on stochastic computingDaewoo Kim, Mansureh S. Moghaddam, Hossein Moradian, Hyeon Uk Sim, Jongeun Lee, Kiyoung Choi. 287-290 [doi]
• All binarized convolutional neural network and its implementation on an FPGAMasayuki Shimoda, Shimpei Sato, Hiroki Nakahara. 291-294 [doi]
• FPGA-based accelerator for losslessly quantized convolutional neural networksMankit Sit, Ryosuke Kazami, Hideharu Amano. 295-298 [doi]
• FPGA implementation of a real-time super-resolution system with a CNN based on a residue number systemTaito Manabe, Yuichiro Shibata, Kiyoshi Oguri. 299-300 [doi]
• A unified reconfigurable floating-point arithmetic architecture based on CORDIC algorithmBingyi Li, Linlin Fang, Yizhuang Xie, He Chen, Liang Chen. 301-302 [doi]