Erik H. D'Hollander - researchr alias

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Viewing Publication 1 - 17 from 17

2023

ZyPy: Intercepting NumPy operations for acceleration on FPGAsGerbrand De Laender, Erik H. D'Hollander. HEART 2023: 100-106 [doi]

2019

Empowering Parallel Computing with Field Programmable Gate ArraysErik H. D'Hollander. parco 2020: 16-31 [doi]

Mapping a Guided Image Filter on the HARP Reconfigurable Architecture Using OpenCLThomas Faict, Erik H. D'Hollander, Bart Goossens. algorithms, 12(8):149, 2019. [doi]

2018

Heterogeneous Cloud Computing: Design Methodology to Combine Hardware AcceleratorsBruno da Silva, Jan G. Cornelis, An Braeken, Erik H. D'Hollander, Jan Lemeire, Abdellah Touhafi. cloudtech 2018: 1-8 [doi]

2017

Calling hardware procedures in a reconfigurable accelerator using RPC-FPGAErik H. D'Hollander, Bruno Chevalier, Koen De Bosschere. fpt 2017: 271-274 [doi]

ParaFPGA 2017: Enlarging the Scope of Parallel Programming with FPGAsErik H. D'Hollander, Abdellah Touhafi. parco 2018: 619-621 [doi]

2016

High-Level Synthesis Optimization for Blocked Floating-Point Matrix MultiplicationErik H. D'Hollander. sigarch, 44(4):74-79, 2016. [doi]

2015

ParaFPGA15: Exploring threads and trends in programmable hardwareErik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi. parco 2016: 501-504 [doi]

2013

ParaFPGA 2013: Harnessing Programs, Power and Performance in Parallel FPGA applicationsErik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi. parco 2014: 493-496 [doi]

Performance and Resource Modeling for FPGAs using High-Level Synthesis toolsBruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi. parco 2014: 523-531 [doi]

Performance Modeling for FPGAs: Extending the Roofline Model with High-Level Synthesis ToolsBruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi. ijrc, 2013, 2013. [doi]

Performance and toolchain of a combined GPU/FPGA desktop (abstract only)Bruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire. fpga 2013: 274 [doi]

Comparing and combining GPU and FPGA accelerators in an image processing contextBruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire. fpl 2013: 1-4 [doi]

2012

Performance and Programming Environment of a Combined GPU/FPGA DesktopBruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire. hpc 2013: 177-193 [doi]

2011

ParaFPGA 2011 High Performance Computing with Multiple FPGAs: Design Methodology and ApplicationsErik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi. parco 2012: 575-577 [doi]

2009

ParaFPGA: Parallel Computing with Flexible HardwareErik H. D'Hollander, Dirk Stroobandt, Abdellah Touhafi. parco 2010: 581-583 [doi]

2008

Refactoring Intermediately Executed Code to Reduce Cache Capacity MissesKristof Beyls, Erik H. D'Hollander. jilp, 10, 2008. [doi]

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