Abstract is missing.
- Criticality-based routing for FPGAS with reverse body bias switch box architecturesWei Ting Loke, Wenfeng Zhao, Yajun Ha. 1-6 [doi]
- A run-time graph-based Polynomial Placement and routing algorithm for virtual FPGASRicardo S. Ferreira, L. Rocha, A. Santos, J. Nacif, Stephan Wong, Luigi Carro. 1-8 [doi]
- Generating infrastructure for FPGA-accelerated applicationsMyron King, Asif Khan, Abhinav Agarwal, Oriol Arcas, Arvind. 1-6 [doi]
- Analysis of matrix multiplication on high density Virtex-7 FPGAWilson Jose, Ana Rita Silva, Horácio C. Neto, Mário P. Véstias. 1-4 [doi]
- Distributed embedded systems design using Petri netsFilipe Moutinho, Luís Gomes. 1-2 [doi]
- Compact implementation of CCM and GCM modes of AES using DSP blocksAntonio De La Piedra, Abdellah Touhafi, An Braeken. 1-4 [doi]
- Integration of a multi-FPGA system in a common cluster environmentOliver Knodel, Rainer G. Spallek. 1-2 [doi]
- Hardware-accelerated regular expression matching for high-throughput text analyticsKubilay Atasu, Raphael Polig, Christoph Hagleitner, Frederick R. Reiss. 1-7 [doi]
- Analyzing the thermal hotspots in FPGA-based embedded systemsHussam Amrouch, Thomas Ebi, Josef Schneider, Sridevan Parameswaran, Jörg Henkel. 1-4 [doi]
- Design of a multi GBPS Single Carrier digital baseband for 60GHz applications and its FPGA implementationSurendra Guntur, Feike Jansen, Jan Hoogerbrugge, Lotfi Abkari, Eric Vos. 1-4 [doi]
- A single-precision compressive sensing signal reconstruction engine on FPGAsFengbo Ren, Richard Dorrance, Wenyao Xu, Dejan Markovic. 1-4 [doi]
- Dependable Dynamic Partial Reconfiguration with minimal area & time overheads on Xilinx FPGASStefano Di Carlo, Giulio Gambardella, Marco Indaco, Paolo Prinetto, Daniele Rolfo, Pascal Trotta. 1-4 [doi]
- Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CADMeng Yang, Jinmei Lai, Jiarong Tong. 1-4 [doi]
- Arithmetic core generation using bit heapsNicolas Brunie, Florent de Dinechin, Matei Istoan, Guillaume Sergent, Kinga Illyes, Bogdan Popa. 1-8 [doi]
- Identifying sequences of optimizations for HW/SW compilationRicardo Nobre. 1-2 [doi]
- A CMOS Field Programmable Analog Array for intelligent sensory applicationXiaoyan Cheng, Tao Yin, Qisong Wu, Yiping Jia, Haigang Yang. 1-4 [doi]
- High performance architecture for object detection in streamed videosPavel Zemcík, Roman Juránek, Petr Musil, Martin Musil, Michal Hradis. 1-4 [doi]
- A hardware accelerated approach for imaging flow cytometryDajung Lee, Pingfan Meng, Matthew Jacobsen, Henry Tse, Dino Di Carlo, Ryan Kastner. 1-8 [doi]
- Accelerating solvers for global atmospheric equations through mixed-precision data flow engineLin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang. 1-6 [doi]
- On measurement of parameters of programmable microelectronic nanostructures under accelerating extreme conditions (Xilinx 28nm XC7Z020 Zynq FPGA)Petr Pfeifer, Zdenek Plíva. 1-4 [doi]
- High performance FPGA object detector: Hardware prototypePavel Zemcík, Roman Juránek, Petr Musil, Martin Musil, Michal Hradis. 1 [doi]
- FPGA based hardware-software co-designed dynamic binary translation systemYuan Yao, Zhongyong Lu, Qingsong Shi, Wenzhi Chen. 1-4 [doi]
- Parallel and scalable custom computing for real-time fluid simulation on a cluster node with four tightly-coupled FPGAsKentaro Sano, Ryo Ito, Hayato Suzuki, Yoshiaki Kono. 1 [doi]
- A high-performance IPV6 lookup engine on FPGAThilan Ganegedara, Viktor K. Prasanna. 1-4 [doi]
- Generation of multi-core systems from multithreaded softwareAlexander Wold, Jim Torresen, Andreas Agne. 1-4 [doi]
- Comparing and combining GPU and FPGA accelerators in an image processing contextBruno da Silva, An Braeken, Erik H. D'Hollander, Abdellah Touhafi, Jan G. Cornelis, Jan Lemeire. 1-4 [doi]
- MAMPSX: A demonstration of rapid, predictable HMPSOC synthesisShakith Fernando, Mark Wijtvliet, Firew Siyoum, Yifan He, Sander Stuijk, Akash Kumar, Henk Corporaal. 1 [doi]
- A FPGA design for high speed feature extraction from a compressed measurement streamDustin Richmond, Ryan Kastner, Ali Irturk, John McGarry. 1-8 [doi]
- A hardware complete detection mechanism for an energy efficient reconfigurable accelerator CMAAkihito Tsusaka, Mai Izawa, Rie Uno, Nobuyuki Ozaki, Hideharu Amano. 1-4 [doi]
- An event-based middleware for the remote management of runtime hardware reconfigurationFrançois Philipp, Manfred Glesner. 1-4 [doi]
- A flexible hash table design for 10GBPS key-value stores on FPGASZsolt István, Gustavo Alonso, Michaela Blott, Kees A. Vissers. 1-8 [doi]
- The study of three-dimensional multiphase-flow simulatorKenta Fujinami, Yoshiki Yamaguchi, Akira Sugiura, Yuetsu Kodama. 1-4 [doi]
- The power of communication: Energy-efficient NOCS for FPGASMohamed S. Abdelfattah, Vaughn Betz. 1-8 [doi]
- In pursuit of instant gratification for FPGA designAndrew Love, Wenwei Zha, Peter Athanas. 1-8 [doi]
- Building partial systems with GoAheadChristian Beckhoff, Alexander Wold, Anders Fritzell, Dirk Koch, Jim Torresen. 1 [doi]
- Defect-robust FPGA architectures for intellectual property cores in system LSIMotoki Amagasaki, Kazuki Inoue, Qian Zhao, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 1-7 [doi]
- Token-based dictionary pattern matching for text analyticsRaphael Polig, Kubilay Atasu, Christoph Hagleitner. 1-6 [doi]
- Towards bounded error recovery time in FPGA-based TMR circuits using dynamic partial reconfigurationEdiz Cetin, Oliver Diessel, Lingkan Gong, Victor Lai. 1-4 [doi]
- Run-time optimization of a dynamically reconfigurable embedded system through performance predictionGiovanni Mariani, Vlad Mihai Sima, Gianluca Palermo, Vittorio Zaccaria, Giacomo Marchiori, Cristina Silvano, Koen Bertels. 1-8 [doi]
- A high-performance overlay architecture for pipelined execution of data flow graphsDavor Capalija, Tarek S. Abdelrahman. 1-8 [doi]
- FPGA-based K-means clustering using tree-based data structuresFelix Winterstein, Samuel Bayliss, George A. Constantinides. 1-6 [doi]
- Improving autonomous soft-error tolerance of FPGA through LUT configuration bit manipulationAnup Das, Shyamsundar Venkataraman, Akash Kumar. 1-8 [doi]
- FPGA based Rekeying for cryptographic key management in Storage Area NetworkYi Wang, Yajun Ha. 1-6 [doi]
- TputCache: High-frequency, multi-way cache for high-throughput FPGA applicationsAaron Severance, Guy G. F. Lemieux. 1-6 [doi]
- SMI: Slack Measurement Insertion for online timing monitoring in FPGAsJoshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung. 1-4 [doi]
- Automated synthesis of FPGA-based heterogeneous interconnect topologiesAlessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo. 1-8 [doi]
- Energy efficient architecture for matrix multiplication on FPGAsKiran Kumar Matam, Hoang Le, Viktor K. Prasanna. 1-4 [doi]
- A resource-efficient probabilistic fault simulatorDavid May, Walter Stechele. 1-4 [doi]
- A self-adaptive image processing application based on evolvable and scalable hardwareAngel Gallego, Javier Mora, Andrés Otero, Blanca Lopez, Eduardo de la Torre, Teresa Riesgo. 1 [doi]
- Binarization based implementation for real-time human detectionShuai Xie, Yibin Li, Zhiping Jia, Lei Ju. 1-4 [doi]
- Hardware-efficient implementation of a Femtocell/Macrocell interference-mitigation technique for high-performance LTE-based systemsOriol Font-Bach, Nikolaos G. Bartzoudis, Miquel Payaró, Antonio Pascual-Iserte. 1-4 [doi]
- Iterative floating point computation using FPGA DSP blocksFredrik Brosser, Hui Yan Cheah, Suhaib A. Fahmy. 1-6 [doi]
- Optimizing under abstraction: Using prefetching to improve FPGA performanceHsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer. 1-8 [doi]
- The HercuLeS high-level synthesis environmentNikolaos Kavvadias, Kostas Masselos. 1 [doi]
- A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualizationHarry Sidiropoulos, Peter Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker. 1-4 [doi]
- FPGA IP protection by binding Finite State Machine to Physical Unclonable FunctionJiliang Zhang, Yaping Lin, Yongqiang Lyu, Gang Qu, Ray C. C. Cheung, Wenjie Che, Qiang Zhou, Jinian Bian. 1-4 [doi]
- Efficient floating-point polynomial evaluation on FPGASMartin Langhammer, Bogdan Pasca. 1-6 [doi]
- Timing driven RTL-to-RTL partitioner for multi-FPGA systemsTobias Strauch. 1-4 [doi]
- Dynamic branch prediction for high-level synthesisVianney Lapotre, Philippe Coussy, Cyrille Chavet, Hugues Wouafo, Robin Danilo. 1-6 [doi]
- A 64-bit MIPS processor running freebsd on a portable FPGA tabletJonathan Woodruff, A. Theodore Markettos, Simon W. Moore. 1 [doi]
- A variation-adaptive retiming method exploiting reconfigurabilityZhenyu Guan, Justin S. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung. 1-4 [doi]
- A space/time tradeoff methodology using higher-order functionsRinse Wester, Jan Kuper. 1-2 [doi]
- Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGASMichael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele. 1-8 [doi]
- Weasel: A platform-independent streaming-optimized SATA controllerPatrick Lehmann, Thomas Frank, Oliver Knodel, Steffen Köhler, Thomas B. Preußer, Rainer G. Spallek. 1-4 [doi]
- An open-source multi-FPGA modular system for fair benchmarking of True Random Number GeneratorsViktor Fischer, Florent Bernard, Patrick Haddad. 1-4 [doi]
- A reconfigurable computing architecture using magnetic tunneling junction memoriesVictor Silva, Jorge R. Fernandes, Mário P. Véstias, Horácio C. Neto. 1-2 [doi]
- A dataflow-inspired CGRA for streaming applicationsAnja Niedermeier, Jan Kuper, Gerard J. M. Smit. 1-2 [doi]
- Hybrid FPGA-accelerated SQL query processingLouis Woods, Zsolt István, Gustavo Alonso. 1 [doi]
- Rapid FPGA design prototyping through preservation of system logic: A case studyTravis Haroldsen, Brent E. Nelson, Brad White. 1-7 [doi]
- Staticroute: A novel router for the Dynamic Partial Reconfiguration of FPGASBrahim Al Farisi, Karel Bruneel, Dirk Stroobandt. 1-7 [doi]
- A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithmChin Hau Hoo, Yajun Ha, Akash Kumar. 1-4 [doi]
- FEMIP: A high performance FPGA-based features extractor & matcher for space applicationsStefano Di Carlo, Giulio Gambardella, Paolo Prinetto, Daniele Rolfo, Pascal Trotta, Piegiorgio Lanza. 1-4 [doi]
- Simulation-based HW/SW co-debugging for field-programmable systems-on-chipRuediger Willenberg, Paul Chow. 1-8 [doi]
- A digital architecture for real-time nonuniformity correction of infrared focal-plane arraysRodolfo Redlich, Miguel Figueroa. 1-4 [doi]
- Fast, FPGA-based Rainbow Table creation for attacking encrypted mobile communicationsPanagiotis Papantonakis, Dionisios N. Pnevmatikatos, Ioannis Papaefstathiou, Charalampos Manifavas. 1-6 [doi]
- Design and FPGA implementation of a 100 Gbit/s optical transport network processorRodrigo Bernardo, Arley H. Salvador, Eduardo Mobilon, Luis R. Monte, Stephane Boisclair, Avrum Warshawsky. 1-4 [doi]
- A scalable design approach for stencil computation on reconfigurable clustersXinyu Niu, José Gabriel F. Coutinho, Wayne Luk. 1-4 [doi]
- Design Space Exploration based on multiobjective genetic algorithms and clustering-based high-level estimationLuiz G. A. Martins, Eduardo Marques. 1-2 [doi]
- FPGA based control for real time systemsShane T. Fleming, David B. Thomas. 1-2 [doi]
- Impact of hard macro size on FPGA clock rate and place/route timeChristopher Lavin, Brent E. Nelson, Brad L. Hutchings. 1-6 [doi]
- Pipelining computing stages in configurable multicore architecturesAli Azarian. 1-2 [doi]
- Bambu: A modular framework for the high level synthesis of memory-intensive applicationsChristian Pilato, Fabrizio Ferrandi. 1-4 [doi]
- FPGA implementation and DPA resistance analysis of a lightweight HMAC construction based on photon hash familySusana Eiroa, Iluminada Baturone. 1-4 [doi]
- Scalable and high throughput biosensing platformJosé Leitão, Jose Germano, Nuno Roma, Ricardo Chaves, Pedro Tomás. 1-6 [doi]
- High-level synthesis with behavioral level multi-cycle path analysisHongbin Zheng, Swathi T. Gurumani, Liwei Yang, Deming Chen, Kyle Rupnow. 1-8 [doi]
- Magnitude modulation on reconfigurable computing devicesMarco Alexandre Cravo Gomes, Vítor Manuel Mendes da Silva, Ricardo Ferrao. 1-4 [doi]
- FPGA-accelerated sliding window classifier with structured featuresOndrej Sychrovsky, Martin Matousek, Radim Sára. 1-4 [doi]
- A fully pipelined FPGA architecture for stochastic simulation of chemical systemsDavid B. Thomas, Hideharu Amano. 1-7 [doi]
- Energy efficient parameterized FFT architectureRen Chen, Hoang Le, Viktor K. Prasanna. 1-7 [doi]
- Accelerating Random Forest training process using FPGAChuan Cheng, Christos-Savvas Bouganis. 1-7 [doi]
- Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM)Zahid Ullah, Manish Kumar Jaiswal, Ray C. C. Cheung. 1-4 [doi]
- A high performance deblocking filter hardware for High Efficiency Video CodingErdem Ozcan, Yusuf Adibelli, Ilker Hamzaoglu. 1-4 [doi]
- Aging monitoring with local sensors in FPGA-based designsCarlos Leong, Jorge Semião, Isabel C. Teixeira, Marcelino B. Santos, João Paulo Teixeira, M. Valdes, Judit Freijedo, Juan J. Rodríguez-Andina, Fabian Vargas. 1-4 [doi]
- Low-cost, high-performance branch predictors for soft processorsDi Wu, Kaveh Aasaraai, Andreas Moshovos. 1-6 [doi]
- Shared memory heterogeneous computation on PCIe-supported platformsSambit K. Shukla, Yang Yang, Laxmi N. Bhuyan, Philip Brisk. 1-4 [doi]
- Accurate and flexible flow-based monitoring for high-speed networksMarco Forconesi, Gustavo Sutter, Sergio López-Buedo, Javier Aracil. 1-4 [doi]
- FPGA implementation of Hierarchical Enumerative Coding for locally stationary image sourceYuhui Bai, Syed Zahid Ahmed, Bertrand Granado. 1-6 [doi]
- Should FPGAS abandon the pass-gate?Charles Chiasson, Vaughn Betz. 1-8 [doi]
- A framework for hardware cellular genetic algorithms: An application to spectrum allocation in cognitive radioPedro Vieira dos Santos, José Carlos Alves, João Canas Ferreira. 1-4 [doi]
- SDR control interface: An FPGA based infrastructure for control of VPX Software Defined Radio systemsStefanie Castillo, Armando Astarloa, Jesús Lázaro, Sergio Salas, Isaac Ballesteros. 1-4 [doi]
- Timing-constrained minimum area/power FPGA memory mappingFangqing Du, Colin Yu Lin, Xiuhai Cui, Jiabin Sun, Feng Liu, Fei Liu, Haigang Yang. 1-4 [doi]
- Radiation mitigation efficiency of scrubbing on the FPGA based CBM-TOF read-out controllerSebastian Manz, Jano Gebelein, Andrei Oancea, Heiko Engel, Udo Kebschull. 1-6 [doi]
- RIFFA 2.0: A reusable integration framework for FPGA acceleratorsMatthew Jacobsen, Ryan Kastner. 1-8 [doi]
- Performance evaluation of Sparse Matrix-Matrix MultiplicationShweta Jain-Mendon, Ron Sass. 1-4 [doi]
- Managing the FPGA memory wall: Custom computing or vector processing?Matthew Naylor, Paul J. Fox, A. Theodore Markettos, Simon W. Moore. 1-6 [doi]
- A novel net-partition-based multithread FPGA routing methodChun Zhu, Jian Wang, Jinmei Lai. 1-4 [doi]
- K) multipliers on FPGASMiguel Morales-Sandoval, Arturo Diaz-Perez. 1-6 [doi]
- Titan: Enabling large and complex benchmarks in academic CADKevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz. 1-8 [doi]
- Accelerating maximum likelihood estimation for Hawkes point processesCe Guo, Wayne Luk. 1-6 [doi]
- Towards a many-core architecture for HPCJanet Wyngaard, Michael Inggs, John Collins, Brian Farrimond. 1-4 [doi]
- Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling linksYusuke Koizumi, Noriyuki Miura, Yasuhiro Take, Hiroki Matsutani, Tadahiro Kuroda, Hideharu Amano, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, Hiroshi Nakamura. 1 [doi]
- Degradation in FPGAs: Monitoring, modeling and mitigation (PHD forum paper: Thesis broad overview)Abdulazim Amouri, Mehdi Baradaran Tahoori. 1-2 [doi]
- An efficient FPGA overlay for portable custom instruction set extensionsDirk Koch, Christian Beckhoff, Guy G. F. Lemieux. 1-8 [doi]
- Memory efficient IP lookup in 100 GBPS networksJirí Matousek, Martin Skacan, Jan Korenek. 1-8 [doi]
- Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGASKarel Heyse, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, Dirk Stroobandt. 1-8 [doi]
- An asynchronous bus bridge for partitioned multi-soc architectures on FPGAsDaniel Kliem, Sven-Ole Voigt. 1-4 [doi]
- NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstractStuart Byma, J. Gregory Steffan, Paul Chow. 1 [doi]
- Altering LUT configuration for wear-out mitigation of FPGA-mapped designsParthasarathy M. B. Rao, Abdulazim Amouri, Saman Kiamehr, Mehdi Baradaran Tahoori. 1-8 [doi]
- Multiple constant multiplication with ternary addersMartin Kumm, Martin Hardieck, Jens Willkomm, Peter Zipf, Uwe Meyer-Baese. 1-8 [doi]
- SimXMD: Simulation-based HW/SW co-debuggingRuediger Willenberg, Paul Chow. 1 [doi]
- A packet classifier using LUT cascades based on EVMDDS (k)Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura. 1-6 [doi]
- Shadow And-Inverter ConesHadi Parandeh-Afshar, Grace Zgheib, David Novo, Madhura Purnaprajna, Paolo Ienne. 1-4 [doi]
- Charge recycling for power reduction in FPGA interconnectSafeen Huda, Jason Helge Anderson, Hirotaka Tamura. 1-8 [doi]
- A spiking neural network on a portable FPGA tabletMatthew Naylor, Paul J. Fox, A. Theodore Markettos, Simon W. Moore. 1 [doi]
- Aging-based leakage energy reduction in FPGAsSheng Wei, Jason Xin Zheng, Miodrag Potkonjak. 1-4 [doi]
- IOPT-tools - A Web based tool framework for embedded systems controller development using Petri netsLuís Gomes, Filipe Moutinho, Fernando Pereira. 1 [doi]
- Remote FPGA design through eDiViDe - European Digital Virtual Design LabJ. Vandorpe, Jo Vliegen, R. Smeets, Nele Mentens, Milos Drutarovský, Michal Varchola, K. Lemke-Rust, P. Ploger, P. Samarin, D. Koch, Y. Hafting, J. Torresen. 1 [doi]
- Fast dynamically updatable packet classifier on FPGAYun R. Qu, Viktor K. Prasanna. 1-4 [doi]
- A low-complexity implementation of QC-LDPC encoder in reconfigurable logicGeorgios Tzimpragos, Christoforos Kachris, Dimitrios Soudris, Ioannis Tomkos. 1-4 [doi]
- An automatic FPGA design and implementation frameworkQian Zhao, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi. 1-4 [doi]
- A hardware security scheme for RRAM-based FPGAYi-Chung Chen, Wei Zhang, Hai Helen Li. 1-4 [doi]
- Rapid modular assembly of Xilinx FPGA designsAndrew Love, Peter Athanas. 1 [doi]
- From Quartus to VPR: Converting HDL to BLIF with the Titan flowKevin E. Murray, Scott Whitty, Suya Liu, Jason Luu, Vaughn Betz. 1 [doi]
- Accelerated FPGA repair through shifted scrubbingGabriel L. Nazar, Leonardo P. Santos, Luigi Carro. 1-6 [doi]
- Image recognition operation on a dynamically reconfigurable vison architectureYuki Kamikubo, Minoru Watanabe, Shoji Kawahito. 1-4 [doi]
- Runtime assertions and exceptions for streaming systemsTim Todman, Wayne Luk. 1-4 [doi]
- TILT: A multithreaded VLIW soft processor familyKalin Ovtcharov, Ilian Tili, J. Gregory Steffan. 1-4 [doi]
- A secure coprocessor for database applicationsArvind Arasu, Ken Eguro, Raghav Kaushik, Donald Kossmann, Ravi Ramamurthy, Ramarathnam Venkatesan. 1-8 [doi]