Qiang Wang 0006 - researchr alias

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Viewing Publication 1 - 7 from 7

2025

An Adaptive 56-Gb/s Duo-PAM4 Detector Using Reduced Branch Maximum Likelihood Sequence Detection in a 28-nm CMOS Wireline ReceiverMingche Lai, Chaolong Xu, Fangxu Lv, Jiaqing Xu, Qiang Wang 0006, Yang Ou, Xiaoyue Hu, Cewen Liu, Zhouhao Yang. tcasI, 72(4):1866-1877, April 2025. [doi]

A high speed adaptive reflection cancellation equalization circuit with Floating Tap FFE and Loop-Refactored DFE for ADC-DSP-based wireline receiverCewen Liu, Xingyun Qi, Fangxu Lv, Qiang Wang 0006, Liquan Xiao, Xiaoyue Hu, Chaolong Xu, Zhouhao Yang, Meng Li, Mingche Lai. mj, 159:106612, 2025. [doi]

A Novel High-Speed Adaptive Duobinary Digital Detector Based on the Feed-Forward Equalizer and the Maximum Likelihood Sequence Detector for Wireline TransceiversChaolong Xu, Fangxu Lv, Mingche Lai, Xingyun Qi, Qiang Wang 0006, Zhang Luo, Shijie Li, Geng Zhang 0001. tvlsi, 33(4):1042-1052, April 2025. [doi]

2024

A reduced complexity MLSD-based adaptive Duo-PAM4 detector in 28-nm CMOS for 56-Gb/s wireline receiverChaolong Xu, Fangxu Lv, Mingche Lai, Zhang Luo, Xingyun Qi, Jiaqing Xu, Qiang Wang 0006, Liquan Xiao, Cewen Liu, Hua Xu. asscc 2024: 1-3 [doi]

2020

q-Norm Sample-Adaptive Multiple Kernel LearningQiang Wang 0006, Xinwang Liu, Jiaqing Xu. access, 8:39428-39438, 2020. [doi]

2017

An FPGA-based processor for training convolutional neural networksZhiqiang Liu, Yong Dou, Jingfei Jiang, Qiang Wang 0006, Paul Chow. fpt 2017: 207-210 [doi]

2015

Accelerating Molecular Dynamics Simulations on Heterogeneous ArchitectureYueqing Wang, Yong Dou, Song Guo, Yuanwu Lei, Baofeng Li, Qiang Wang 0006. nccet 2016: 118-132 [doi]

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