Table of Contents

• Built for the Edge: The Next-Generation Intel® Xeon D 2700 & 1700 processorsPraveen Mosur. 1-15 [doi]
• Large-scale Graph Neural Network Services through Computational SSD and In-Storage Processing ArchitecturesMiryeong Kwon, Donghyun Gouk, Sangwon Lee, Myoungsoo Jung. 1-25 [doi]
• AMD 400G Adaptive SmartNIC SoC: Technology previewJaideep Dastidar, David Riddoch, Jason Moore, Steve Pope, Jim Wesselkamper. 1-31 [doi]
• DSPU: A 281.6mW Real-Time Deep Learning-Based Dense RGB-D Data Acquisition with Sensor Fusion and 3D Perception System-on-ChipDongseok Im, Gwangtae Park, Zhiyong Li, Junha Ryu, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, Hoi-Jun Yoo. 1-25 [doi]
• Neuro-CIM: A 310.4 TOPS/W Neuromorphic Computing-in-Memory Processor with Low WL/BL activity and Digital-Analog Mixed-mode Neuron FiringSangyeob Kim, Sangjin Kim, Soyeon Um, Soyeon Kim, Kwantae Kim, Hoi-Jun Yoo. 1-25 [doi]
• Enabling Scalable Application-Specific Optical Engines (ASOE) by Monolithic Integration of Photonics and ElectronicsChristoph Schulien. 1-32 [doi]
• Heterogenous Integration Enables FPGA Based Hardware Acceleration for RF ApplicationsSergey Y. Shumarayev, Allen Chan, Tim Hoang, Robert Keller. 1-20 [doi]
• Meteor Lake and Arrow Lake Intel Next-Gen 3D Client Architecture Platform with FoverosWilfred Gomes, Slade Morgan, Boyd Phelps, Tim Wilson, Erik Hallnor. 1-40 [doi]
• HNPU-V2: A 46.6 FPS DNN Training Processor for Real-World Environmental Adaptation based Robust Object Detection on Mobile DevicesDonghyeon Han, Dongseok Im, Gwangtae Park, YoungWoo Kim, Seokchan Song, Juhyoung Lee, Hoi-Jun Yoo. 1-18 [doi]
• NVIDIA ORIN System-On-ChipMichael Ditty. 1-17 [doi]
• A 13.7μJ/prediction 88% Accuracy CIFAR-10 Single-Chip Wired-logic Processor in 16-nm FPGA using Non-Linear Neural NetworkYao-Chung Hsu, Atsutake Kosuge, Rei Sumikawa, Kota Shiba, Mototsugu Hamada, Tadahiro Kuroda. 1-14 [doi]
• VTA-NIC: Deep Learning Inference Serving in Network Interface CardsKenji Tanaka, Yuki Arikawa, Kazutaka Morita, Tsuyoshi Ito, Takashi Uchida, Natsuko Saito, Shinya Kaji, Takeshi Sakamoto. 1-16 [doi]
• 壁仞™ BR100 GPGPU: Accelerating Datacenter Scale AI ComputingMike Hong, Lingjie Xu. 1-22 [doi]
• DOJO: The Microarchitecture of Tesla's Exa-Scale ComputerEmil Talpes, Douglas Williams, Debjit Das Sarma. 1-28 [doi]
• Dimensity 9000 - A Flagship Smartphone SoCMediatek Ericbill Wang, Arm Stefan Rosinger, Saurabh Pradhan. 1-23 [doi]
• System Architecture and Software Stack for GDDR6-AiMYongkee Kwon, Kornijcuk Vladimir, Nahsung Kim, Woojae Shin, Jongsoon Won, Minkyu Lee, Hyunha Joo, Haerang Choi, Guhyun Kim, Byeongju An, Jeongbin Kim, Jaewook Lee, Ilkon Kim, Jaehan Park, Chanwook Park, Yosub Song, Byeongsu Yang, Hyungdeok Lee, Seho Kim, DaeHan Kwon, Seong Ju Lee, Kyuyoung Kim, Sanghoon Oh, Joonhong Park, Gimoon Hong, Dongyoon Ka, Kyudong Hwang, Jeongje Park, Kyeong Pil Kang, Jungyeon Kim, Junyeol Jeon, Myeongjun Lee, Minyoung Shin, Minhwan Shin, Jaekyung Cha, Changson Jung, Kijoon Chang, Chunseok Jeong, Euicheol Lim, Il Park 0001, Junhyun Chun. 1-25 [doi]
• Nvidia Hopper GPU: Scaling PerformanceJack Choquette. 1-46 [doi]
• Cerebras Architecture Deep Dive: First Look Inside the HW/SW Co-Design for Deep Learning : Cerebras SystemsSean Lie. 1-34 [doi]
• Kraken: A Direct Event/Frame-Based Multi-sensor Fusion SoC for Ultra-Efficient Visual Processing in Nano-UAVsAlfio Di Mauro, Moritz Scherer, Davide Rossi, Luca Benini. 1-19 [doi]
• Vision Perception Unit: Next-Generation Smart CMOS Image SensorWenqi Ji, Yuxing Han, Jiangtao Wen, Yubin Hu, Futang Wang, Yuze He, Xi Li, Jun Zhang. 1-13 [doi]
• Trinity: End-to-End In-Database Near-Data Machine Learning Acceleration Platform for Advanced Data AnalyticsJi-Hoon Kim, Seunghee Han, Kwanghyun Park 0001, Soo Young Ji, Joo-Young Kim 0001. 1-16 [doi]
• The Groq Software-defined Scale-out Tensor Streaming Multiprocessor : From chips-to-systems architectural overviewDennis Abts, John Kim, Garrin Kimmell, Matthew Boyd, Kris Kang, Sahil Parmar, Andrew C. Ling, Andrew Bitar, Ibrahim Ahmed 0007, Jonathan Ross. 1-69 [doi]
• HALO: A Flexible and Low Power Processing Fabric for Brain-Computer InterfacesAbhishek Bhattacharjee, Rajit Manohar. 1-37 [doi]
• AMD Ryzen™ 6000 Series for Mobile : Technology OverviewJim Gibney. 1-24 [doi]
• Arm Morello Evaluation Platform -Validating CHERI-based Security in a High-performance SystemRichard Grisenthwaite. 1-22 [doi]
• ™ MI200 Series Accelerator and Node ArchitecturesAlan Smith, Norman James. 1-23 [doi]
• Nvidia GraceJonathon Evans. 1-20 [doi]
• Semiconductors Run the World : Hot Chips 2022Pat Gelsinger. 1-19 [doi]
• A Massive-Scale Brain Activity Decoding ChipAmeer Abdelhadi, Eugene Sha, Andreas Moshovos. 1-65 [doi]
• Scaling of Memory Performance and Capacity with CXL Memory ExpanderS. J. Park, H. Kim, K. S. Kim, J. So, J. Ahn, W. J. Lee, D. Kim, Y.-J. Kim, J. Seok, J.-G. Lee, H. Y. Ryu, C.-Y. Lee, J. Prout, K.-C. Ryoo, S. J. Han, M.-K. Kook, J. S. Choi, J. Gim, Y. S. Ki, S. Ryu, C. Park, D.-G. Lee, J. Cho, H. Song, J. Y. Lee. 1-27 [doi]
• 2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous TransceiversKota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda. 1-14 [doi]
• An Efficient High-quality FHD Super-resolution Mobile Accelerator SoC with Hybrid-precision and Energy-efficient CacheZhiyong Li, Sangjin Kim, Dongseok Im, Donghyeon Han, Hoi-Jun Yoo. 1-26 [doi]
• The Nvlink-Network Switch: Nvidia's Switch Chip for High Communication-Bandwidth SuperpodsAlexander Ishii, Ryan Wells. 1-23 [doi]
• LightTrader : World's first AI-enabled High-Frequency Trading Solution with 16 TFLOPS / 64 TOPS Deep Learning Inference AcceleratorsHyunsung Kim, Sungyeob Yoo, Jaewan Bae, Kyeongryeol Bong, Yoonho Boo, Karim Charfi, Hyo-Eun Kim, Hyun Suk Kim, Jinseok Kim, Byungjae Lee, Jaehwan Lee, Myeongbo Shim, Sungho Shin, Jeong-Seok Woo, Joo-Young Kim 0001, Sunghyun Park, Jinwook Oh. 1-10 [doi]
• Accelerating Graphic Rendering on Programmable RISC-V GPUsBlaise Tine, Varun Saxena, Santosh Srivatsan, Joshua R. Simpson, Fadi Alzammar, Liam Paul Cooper, Sam Jijina, Swetha Rajagoplan, Tejaswini Anand Kumar, Jeff Young, Hyesoon Kim. 1-15 [doi]
• Untether Ai : BoqueriaRobert Beachler, Martin Snelgrove. 1-19 [doi]
• Amber: Coarse-Grained Reconfigurable Array-Based SoC for Dense Linear Algebra AccelerationKathleen Feng, Alex Carsello, Taeyoung Kong, Kalhan Koul, Qiaoyi Liu, Jackson Melchert, Gedeon Nyengele, Maxwell Strange, Keyi Zhang, Ankita Nayak, Jeff Setter, James Thomas 0003, Kavya Sreedhar, Po-Han Chen, Nikhil Bhagdikar, Zachary Myers, Brandon D'Agostino, Pranil Joshi, Stephen Richardson, Rick Bahr, Christopher Torng, Mark Horowitz, Priyanka Raina. 1-30 [doi]
• Intel's Ponte Vecchio GPU : Architecture, Systems & SoftwareHong Jiang. 1-29 [doi]
• DFX: A Low-latency Multi-FPGA Appliance for Accelerating Transformer-based Text GenerationSeongmin Hong, Seungjae Moon, Junsoo Kim, Sungjae Lee, Minsub Kim, Dongsoo Lee, Joo-Young Kim. 1-17 [doi]
• From High-Level Frameworks to custom Silicon with SODASerena Curzel, Nicolas Bohm Agostini, Reece Neff, Ankur Limaye, Jeff Jun Zhang, Vinay Amatya, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, David Brooks 0001, Gu-Yeon Wei, Fabrizio Ferrandi, Antonino Tumeo. 1-13 [doi]
• DOJO: Super-Compute System Scaling for ML TrainingBill Chang, Rajiv Kurian, Doug Williams, Eric Quinnell. 1-45 [doi]