Table of Contents

• OLAF'17: Third International Workshop on Overlay Architectures for FPGAsHayden Kwok-Hay So, John Wawrzynek. 1 [doi]
• The Role of FPGAs in Deep LearningAndrew Ling, Jason Anderson. 3 [doi]
• Can FPGAs Beat GPUs in Accelerating Next-Generation Deep Neural Networks?Eriko Nurvitadhi, Ganesh Venkatesh, Jaewoong Sim, Debbie Marr, Randy Huang, Jason Ong Gee Hock, Yeong Tat Liew, Krishnan Srivatsan, Duncan Moss, Suchit Subhaschandra, Guy Boudoukh. 5-14 [doi]
• Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAsRitchie Zhao, Weinan Song, Wentao Zhang, Tianwei Xing, Jeng-Hau Lin, Mani B. Srivastava, Rajesh Gupta, Zhiru Zhang. 15-24 [doi]
• Improving the Performance of OpenCL-based FPGA Accelerator for Convolutional Neural NetworkJialiang Zhang, Jing Li. 25-34 [doi]
• Frequency Domain Acceleration of Convolutional Neural Networks on CPU-FPGA Shared Memory SystemChi Zhang, Viktor K. Prasanna. 35-44 [doi]
• Optimizing Loop Operation and Dataflow in FPGA Acceleration of Deep Convolutional Neural NetworksYufei Ma, Yu Cao, Sarma B. K. Vrudhula, Jae-sun Seo. 45-54 [doi]
• An OpenCL™ Deep Learning Accelerator on Arria 10Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu. 55-64 [doi]
• FINN: A Framework for Fast, Scalable Binarized Neural Network InferenceYaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Philip Heng Wai Leong, Magnus Jahre, Kees A. Vissers. 65-74 [doi]
• ESE: Efficient Speech Recognition Engine with Sparse LSTM on FPGASong Han, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang, Huazhong Yang, William (Bill) J. Dally. 75-84 [doi]
• Quality-Time Tradeoffs in Component-Specific Mapping: How to Train Your Dynamically Reconfigurable Array of Gates with Outrageous Network-delaysHans Giesen, Raphael Rubin, Benjamin Gojman, André DeHon. 85-94 [doi]
• Synchronization Constraints for Interconnect SynthesisAlex Rodionov, Jonathan Rose. 95-104 [doi]
• Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic ExpansionMinghua Shen, Guojie Luo. 105-114 [doi]
• Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture ExplorationSadegh Yazdanshenas, Kosuke Tatsumura, Vaughn Betz. 115-124 [doi]
• Automatic Construction of Program-Optimized FPGA Memory NetworksHsin-Jung Yang, Kermin Fleming, Felix Winterstein, Annie I. Chen, Michael Adler, Joel S. Emer. 125-134 [doi]
• NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic ElementZhihong Huang, Xing Wei, Grace Zgheib, Wei Li, Yu Lin, Zhenghong Jiang, Kaihui Tu, Paolo Ienne, Haigang Yang. 135-140 [doi]
• 120-core microAptiv MIPS Overlay for the Terasic DE5-NET FPGA boardChethan Kumar H. B, Prashant Ravi, Gourav Modi, Nachiket Kapre. 141-146 [doi]
• A Parallelized Iterative Improvement Approach to Area Optimization for LUT-Based Technology MappingGai Liu, Zhiru Zhang. 147-156 [doi]
• A Parallel Bandit-Based Approach for Autotuning FPGA CompilationChang Xu, Gai Liu, Ritchie Zhao, Stephen Yang, Guojie Luo, Zhiru Zhang. 157-166 [doi]
• FPGAs in the CloudGeorge A. Constantinides. 167 [doi]
• Hardware Synthesis of Weakly Consistent C ConcurrencyNadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides. 169-178 [doi]
• A New Approach to Automatic Memory Banking using Trace-Based Address MiningYuan Zhou, Khalid Musa Al-Hawaj, Zhiru Zhang. 179-188 [doi]
• Dynamic Hazard Resolution for Pipelining Irregular Loops in High-Level SynthesisSteve Dai, Ritchie Zhao, Gai Liu, Shreesha Srinath, Udit Gupta, Christopher Batten, Zhiru Zhang. 189-194 [doi]
• Accelerating Face Detection on Programmable SoC Using C-Based SynthesisNitish Kumar Srivastava, Steve Dai, Rajit Manohar, Zhiru Zhang. 195-200 [doi]
• Packet Matching on FPGAs Using HMC Memory: Towards One Million RulesDaniel Rozhko, Geoffrey Elliott, Daniel Ly-Ma, Paul Chow, Hans-Arno Jacobsen. 201-206 [doi]
• Boosting the Performance of FPGA-based Graph Processor using Hybrid Memory Cube: A Case for Breadth First SearchJialiang Zhang, Soroosh Khoram, Jing Li. 207-216 [doi]
• ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA ArchitectureGuohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang, Huazhong Yang. 217-226 [doi]
• FPGA-Accelerated Transactional Execution of Graph WorkloadsXiaoyu Ma, Dan Zhang, Derek Chiou. 227-236 [doi]
• Enabling Flexible Network FPGA Clusters in a Heterogeneous Cloud Data CenterNaif Tarafdar, Thomas Lin, Eric Fukuda, Hadi Bannazadeh, Alberto Leon-Garcia, Paul Chow. 237-246 [doi]
• Energy Efficient Scientific Computing on FPGAs using OpenCLDennis Weller, Fabian Oboril, Dimitar Lukarski, Jürgen Becker, Mehdi Baradaran Tahoori. 247-256 [doi]
• Secure Function Evaluation Using an FPGA Overlay ArchitectureXin Fang, Stratis Ioannidis, Miriam Leeser. 257-266 [doi]
• FPGA Acceleration for Computational Glass-Free DisplaysZhuolun He, Guojie Luo. 267-274 [doi]
• Hardware Acceleration of the Pair-HMM Algorithm for DNA Variant CallingSitao Huang, Gowthami Jayashri Manikandan, Anand Ramachandran, Kyle Rupnow, Wen-mei W. Hwu, Deming Chen. 275-284 [doi]
• Measuring the Power-Constrained Performance and Energy Gap between FPGAs and Processors (Abstract Only)Andy Gean Ye, Karthik Ganesan. 285 [doi]
• A Mixed-Signal Data-Centric Reconfigurable Architecture enabled by RRAM Technology (Abstract Only)Yue Zha, Jialiang Zhang, Zhiqiang Wei, Jing Li. 285 [doi]
• A Framework for Iterative Stencil Algorithm Synthesis on FPGAs from OpenCL Programming Model (Abstract Only)Shuo Wang, Yun Liang. 285-286 [doi]
• Thermal Flattening in 3D FPGAs Using Embedded Cooling (Abstract Only)Girish Deshpande, Dinesh Bhatia. 286 [doi]
• A Machine Learning Framework for FPGA Placement (Abstract Only)Gary William Grewal, Shawki Areibi, Matthew Westrik, Ziad Abuowaimer, Betty Zhao. 286 [doi]
• Scala Based FPGA Design Flow (Abstract Only)Yanqiang Liu, Yao Li, Weilun Xiong, Meng Lai, Cheng Chen, Zhengwei Qi, Haibing Guan. 286 [doi]
• Towards Efficient Design Space Exploration of FPGA-based Accelerators for Streaming HPC Applications (Abstract Only)Mostafa Koraei, Magnus Jahre, S. Omid Fatemi. 287 [doi]
• Accurate and Efficient Hyperbolic Tangent Activation Function on FPGA using the DCT Interpolation Filter (Abstract Only)Ahmed M. Abdelsalam, J. M. Pierre Langlois, Farida Cheriet. 287 [doi]
• Precise Coincidence Detection on FPGAs: Three Case Studies (Abstract Only)Ralf Salomon, Ralf Joost. 287 [doi]
• An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only)Thomas Luinaud, Yvon Savaria, J. M. Pierre Langlois. 287-288 [doi]
• Using Vivado-HLS for Structural Design: a NoC Case Study (Abstract Only)Zhipeng Zhao, James C. Hoe. 289 [doi]
• Automatic Generation of Hardware Sandboxes for Trojan Mitigation in Systems on Chip (Abstract Only)Christophe Bobda, Taylor Whitaker, Charles A. Kamhoua, Kevin A. Kwiat, Laurent Njilla. 289 [doi]
• Accelerating Financial Market Server through Hybrid List Design (Abstract Only)Haohuan Fu, Conghui He, Huabin Ruan, Itay Greenspon, Wayne Luk, Yongkang Zheng, Junfeng Liao, Qing Zhang, Guangwen Yang. 289-290 [doi]
• Joint Modulo Scheduling and Memory Partitioning with Multi-Bank Memory for High-Level Synthesis (Abstract Only)Tianyi Lu, Shouyi Yin, Xianqing Yao, Zhicong Xie, Leibo Liu, Shaojun Wei. 290 [doi]
• A 7.663-TOPS 8.2-W Energy-efficient FPGA Accelerator for Binary Convolutional Neural Networks (Abstract Only)Yixing Li, Zichuan Liu, Kai Xu, Hao Yu, Fengbo Ren. 290-291 [doi]
• A Batch Normalization Free Binarized Convolutional Deep Neural Network on an FPGA (Abstract Only)Hiroki Nakahara, Haruyoshi Yonekawa, Hisashi Iwamoto, Masato Motomura. 290 [doi]
• fpgaConvNet: Automated Mapping of Convolutional Neural Networks on FPGAs (Abstract Only)Stylianos I. Venieris, Christos-Savvas Bouganis. 291-292 [doi]
• CPU-FPGA Co-Optimization for Big Data Applications: A Case Study of In-Memory Samtool Sorting (Abstract Only)Jason Cong, Zhenman Fang, Muhuan Huang, Libo Wang, Di Wu 0010. 291 [doi]
• Stochastic-Based Multi-stage Streaming Realization of a Deep Convolutional Neural Network (Abstract Only)Mohammed Alawad, Mingjie Lin. 291 [doi]
• Storage-Efficient Batching for Minimizing Bandwidth of Fully-Connected Neural Network Layers (Abstract Only)Yongming Shen, Michael Ferdman, Peter A. Milder. 293 [doi]
• ASAP: Accelerated Short Read Alignment on Programmable Hardware (Abstract Only)Subho S. Banerjee, Mohamed El-Hadedy, Jong Bin Lim, Daniel Chen, Zbigniew T. Kalbarczyk, Deming Chen, Ravishankar K. Iyer. 293-294 [doi]
• FPGA-based Hardware Accelerator for Image Reconstruction in Magnetic Resonance Imaging (Abstract Only)Emanuele Pezzotti, Alex Iacobucci, Gregory Nash, Umer I. Cheema, Paolo Vinella, Rashid Ansari. 293 [doi]
• RxRE: Throughput Optimization for High-Level Synthesis using Resource-Aware Regularity Extraction (Abstract Only)Atieh Lotfi, Rajesh K. Gupta. 294 [doi]
• GRT 2.0: An FPGA-based SDR Platform for Cognitive Radio Networks (Abstract Only)Haoyang Wu, Tao Wang, Zhiwei Li, Boyan Ding, Xiaoguang Li, Tianfu Jiang, Jun Liu, Songwu Lu. 294-295 [doi]
• FPGA Implementation of Non-Uniform DFT for Accelerating Wireless Channel Simulations (Abstract Only)Srinivas Siripurapu, Aman Gayasen, Padmini Gopalakrishnan, Nitin Chandrachoodan. 295 [doi]
• Cache Timing Attacks from The SoCFPGA Coherency Port (Abstract Only)Sumanta Chaudhuri. 295-296 [doi]
• Learning Convolutional Neural Networks for Data-Flow Graph Mapping on Spatial Programmable Architectures (Abstract Only)Shouyi Yin, Dajiang Liu, Lifeng Sun, Xinhan Lin, Leibo Liu, Shaojun Wei. 295 [doi]
• Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only)Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam. 296 [doi]
• An Energy-Efficient Design-Time Scheduler for FPGAs Leveraging Dynamic Frequency Scaling Emulation (Abstract Only)Wei Ting Loke, Chin Yang Koay. 296 [doi]