Table of Contents

• Meeting with the Forthcoming IC Design The Era of Power, Variability and NRE Explosion and a Bit of the Future Takayasu Sakurai. [doi]
• Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-ChainsRob A. Rutenbar. [doi]
• How Foundry can Help Improve your Bottom-Line? Accuracy Matters!Fu-Chieh Hsu. [doi]
• Model Based Layout Pattern Dependent Metal Filling Algorithm for Improved Chip Surface Uniformity in the Copper ProcessSubarna Sinha, Jianfeng Luo, Charles Chiang. 1-6 [doi]
• Fast and Accurate OPC for Standard-Cell LayoutsDavid M. Pawlowski, Liang Deng, Martin D. F. Wong. 7-12 [doi]
• Coupling-aware Dummy Metal Insertion for LithographyLiang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang. 13-18 [doi]
• Fast Buffer Insertion for Yield Optimization Under Process VariationsRuiming Chen, Hai Zhou. 19-24 [doi]
• A Global Minimum Clock Distribution Network Augmentation Algorithm for Guaranteed Clock Skew YieldBao Liu, Andrew B. Kahng, Xu Xu, Jiang Hu, Ganesh Venkataraman. 24-31 [doi]
• Control-Flow Aware Communication and Conflict Analysis of Parallel ProcessesAxel Siebenborn, Alexander Viehl, Oliver Bringmann, Wolfgang Rosenstiel. 32-37 [doi]
• Software Performance Estimation in MPSoC DesignMárcio Oyamada, Flávio Rech Wagner, Marius Bonaciu, Wander O. Cesário, Ahmed Amine Jerraya. 38-43 [doi]
• Effective OpenMP Implementation and Translation For Multiprocessor System-On-Chip without Using OSWoo-Chul Jeun, Soonhoi Ha. 44-49 [doi]
• Creating Explicit Communication in SoC Models Using Interactive Re-CodingPramod Chandraiah, Junyu Peng, Rainer Dömer. 50-55 [doi]
• System Architecture for Software PeripheralsSiddharth Choudhuri, Tony Givargis. 56-61 [doi]
• A New Boundary Element Method for Multiple-Frequency Parameter Extraction of Lossy SubstratesXiren Wang, Wenjian Yu, Zeyi Wang. 62-67 [doi]
• Hierarchical Optimization Methodology for Wideband Low Noise AmplifiersArthur Nieuwoudt, Tamer Ragheb, Yehia Massoud. 68-73 [doi]
• PLLSim - An Ultra Fast Bang-Bang Phase Locked Loop Simulation ToolMichael Chan, Adam Postula, Yong Ding. 74-79 [doi]
• A Programmable Fully-Integrated GPS receiver in 0.18µm CMOS with Test CircuitsMahta Jenabi, Noushin Riahi, Ali Fotowat Ahmady. 80-85 [doi]
• Ultralow-Power Reconfigurable Computing with Complementary Nano-Electromechanical Carbon Nanotube SwitchesSwarup Bhunia, Massood Tabib-Azar, Daniel G. Saab. 86-91 [doi]
• A 1Tb/s 3W Inductive-Coupling Transceiver ChipNoriyuki Miura, Tadahiro Kuroda. 92-93 [doi]
• 22-29GHz Ultra-Wideband CMOS Pulse Generator for Collision Avoidance Short Range Vehicular Radar SensorsAhmet Oncu, B. B. M. Wasanthamala Badalawa, Tong Wang, Minoru Fujishima. 94-95 [doi]
• A 2.8-V Multibit Complex Bandpass Delta-Sigma-AD Modulator in 0.18µm CMOSHao San, Yoshitaka Jingu, Hiroki Wada, Hiroyuki Hagiwara, Akira Hayakawa, Haruo Kobayashi, Masao Hotta. 96-97 [doi]
• A Wideband CMOS LC-VCO Using Variable InductorK. Ohashi, Y. Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu. 98-99 [doi]
• Design of Active Substrate Noise Canceller using Power Supply di/dt DetectorTaisuke Kazama, Toru Nakura, Makoto Ikeda, Kunihiro Asada. 100-101 [doi]
• A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES InterfacesYu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu. 102-103 [doi]
• Reconfigurable CMOS Low Noise Amplifier Using Variable Bias Circuit for Self CompensationSatoshi Fukuda, D. Kawazoe, Kenichi Okada, Kazuya Masu. 104-105 [doi]
• Psuedo-Millimeter-Wave Up-Conversion Mixer with On-Chip Balun for Vehicular Radar SystemsIvan C. H. Ivan Chee Hong Lai, M. Fujishima. 106-107 [doi]
• Improving Execution Speed of FPGA using Dynamically Reconfigurable TechniqueRoel Pantonial, Md. Ashfaquzzaman Khan, Naoto Miyamoto, Koji Kotani, Shigetoshi Sugawa, Tadahiro Ohmi. 108-109 [doi]
• Single-Issue 1500MIPS Embedded DSP with Ultra Compact CodesLi-Chun Lin, Shih-Hao Ou, Tay-Jyi Lin, Siang-Den Deng, Chih-Wei Liu. 110-111 [doi]
• A Highly Integrated 8mW H.264/AVC Main Profile Real-time CIF Video Decoder on a 16MHz SoC PlatformHuan-Kai Peng, Chun-Hsin Lee, Jian-Wen Chen, Tzu-Jen Lo, Yung-Hung Chang, Sheng-Tsung Hsu, Yuan-Chun Lin, Ping Chao, Wei-Cheng Hung, Kai-Yuan Jan. 112-113 [doi]
• Configurable AMBA On-Chip Real-Time Signal TracerChung-Fu Kao, Chi-Hung Lin, Ing-Jer Huang. 114-115 [doi]
• Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor LogicS. Matsunaga, Takahiro Hanyu, Hiromitsu Kimura, T. Nakamura, H. Takasu. 116-117 [doi]
• A Multi-Drop Transmission-Line Interconnect in Si LSIJunki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu. 118-119 [doi]
• A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS TechnologyTakeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera. 120-121 [doi]
• A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die VariationsYuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera. 122-123 [doi]
• A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSIM. Watanabe, F. Kobayashi. 124-125 [doi]
• Low-Power High-Speed 180-nm CMOS Clock DriversTadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi. 126-127 [doi]
• Fast Analytic Placement using Minimum Cost FlowAmeya R. Agnihotri, Patrick H. Madden. 128-134 [doi]
• FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion ControlNatarajan Viswanathan, Min Pan, Chris C. N. Chu. 135-140 [doi]
• Hippocrates: First-Do-No-Harm Detailed PlacementHaoxing Ren, David Z. Pan, Charles J. Alpert, Gi-Joon Nam, Paul G. Villarrubia. 141-146 [doi]
• ECO-system: Embracing the Change in PlacementJarrod A. Roy, Igor L. Markov. 147-152 [doi]
• Bisection Based Placement for the X ArchitectureSatoshi Ono, Sameer Tilak, Patrick H. Madden. 153-158 [doi]
• Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded SystemsMinje Jun, Kwanhu Bang, Hyuk-Jun Lee, Naehyuck Chang, Eui-Young Chung. 159-164 [doi]
• A Precise Bandwidth Control Arbitration Algorithm for Hard Real-Time SoC BusesBu-Ching Lin, Geeng-Wei Lee, Juinn-Dar Huang, Jing-Yang Jou. 165-170 [doi]
• Communication Architecture Synthesis of Cascaded Bus MatrixJun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi. 171-177 [doi]
• Topology exploration for energy efficient intra-tile communicationJin Guo, Antonis Papanikolaou, Francky Catthoor. 178-183 [doi]
• Application Specific Network-on-Chip Design with Guaranteed Quality Approximation AlgorithmsKrishnan Srinivasan, Karam S. Chatha, Goran Konjevod. 184-190 [doi]
• Thermal-driven Symmetry Constraint for Analog Layout with CBL RepresentationJiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong. 191-196 [doi]
• A Graph Reduction Approach to Symbolic Circuit AnalysisGuoyong Shi, Weiwei Chen, C.-J. Richard Shi. 197-202 [doi]
• Robust Analog Circuit Sizing Using Ellipsoid Method and Affine ArithmeticXuexin Liu, Wai-Shing Luk, Yu Song, PuShan Tang, Xuan Zeng. 203-208 [doi]
• WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory DesignPeng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, PuShan Tang, Xuan Zeng. 209-214 [doi]
• Structured Placement with Topological Regularity EvaluationShigetoshi Nakatake. 215-220 [doi]
• Modeling Sub-90nm On-Chip Variation Using Monte Carlo Method for DFMJun-Fu Huang, Victor C. Y. Chang, Sally Liu, Kelvin Y. Y. Doong, Keh-Jeng Chang. 221-225 [doi]
• DFM reality in sub-nanometer IC designN. Verghese, P. Hurat. 226-231 [doi]
• DFM/DFY practices during physical designs for timing, signal integrity, and powerShi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-Hong Tsai. 232-237 [doi]
• Recent Research and Emerging Challenges in Physical Design for Manufacturability/ReliabilityChung-Wei Lin, Ming-Chao Tsai, Kuang-Yao Lee, Tai-Chen Chen, Ting-Chi Wang, Yao-Wen Chang. 238-243 [doi]
• A Novel Performance-Driven Topology Design AlgorithmMin Pan, Chris C. N. Chu, Priyadarshan Patra. 244-249 [doi]
• FastRoute 2.0: A High-quality and Efficient Global RouterMin Pan, Chris C. N. Chu. 250-255 [doi]
• DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing AlgorithmZhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Lei He, Xianlong Hong. 256-261 [doi]
• A Fast and Stable Algorithm for Obstacle-Avoiding Rectilinear Steiner Minimal Tree ConstructionPei-Ci Wu, Jhih-Rong Gao, Ting-Chi Wang. 262-267 [doi]
• A Theoretical Study on Wire Length Estimation Algorithms for Placement with Opaque BlocksTan Yan, Shuting Li, Yasuhiro Takashima, H. Murata. 268-273 [doi]
• LEAF: A System Level Leakage-Aware Floorplanner for SoCsAseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir. 274-279 [doi]
• Protocol Transducer Synthesis using Divide and Conquer approachShigeru Watanabe, Kenshu Seto, Y. Ishikawa, Satoshi Komatsu, Masahiro Fujita. 280-285 [doi]
• A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional UnitsTakeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai. 286-291 [doi]
• Power and Memory Bandwidth Reduction of an H.264/AVC HDTV Decoder LSI with Elastic Pipeline ArchitectureKentaro Kawakami, Mitsuhiko Kuroda, Hiroshi Kawaguchi, Masahiko Yoshimoto. 292-297 [doi]
• Architectural Optimizations for Text to Speech Synthesis in Embedded SystemsSoumyajit Dey, Monu Kedia, Anupam Basu. 298-303 [doi]
• Deeper Bound in BMC by Combining Constant Propagation and AbstractionRoy Armoni, Limor Fix, Ranan Fraer, Tamir Heyman, Moshe Y. Vardi, Yakir Vizel, Yael Zbar. 304-309 [doi]
• Efficient BMC for Multi-Clock Systems with Clocked SpecificationsMalay K. Ganai, Aarti Gupta. 310-315 [doi]
• Symbolic Model Checking of Analog/Mixed-Signal CircuitsDavid Walter, Scott Little, Nicholas Seegmiller, Chris J. Myers, Tomohiro Yoneda. 316-323 [doi]
• Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware EmulationMarc Boule, Zeljko Zilic. 324-329 [doi]
• Model-based Programming Environment of Embedded Software for MPSoCSoonhoi Ha. 330-335 [doi]
• RTOS and Codesign Toolkit for Multiprocessor Systems-on-ChipShinya Honda, Hiroyuki Tomiyama, Hiroaki Takada. 336-341 [doi]
• Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS SystemsJian-Jia Chen, Chuan-Yue Yang, Tei-Wei Kuo, Chi-Sheng Shih. 342-349 [doi]
• Towards scalable and secure execution platform for embedded systemsHiroaki Inoue, Masato Edahiro, Junji Sakai. 350-354 [doi]
• Passive Interconnect Macromodeling Via Balanced Truncation of Linear Systems in Descriptor FormBoyuan Yan, Sheldon X.-D. Tan, Pu Liu, Bruce McGaughy. 355-360 [doi]
• Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise MethodsS. Dabas, Ning Dong, Jaijeet S. Roychowdhury. 361-366 [doi]
• Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial ChaosYi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheldon X.-D. Tan, Le Kang. 367-372 [doi]
• Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline InterpolationArthur Nieuwoudt, Mehboob Alam, Yehia Massoud. 373-378 [doi]
• Frequency Selective Model Order Reduction via Spectral Zero ProjectionMehboob Alam, Arthur Nieuwoudt, Yehia Massoud. 379-383 [doi]
• Abstract, Multifaceted Modeling of Embedded Processors for System Level DesignGunar Schirner, Andreas Gerstlauer, Rainer Dömer. 384-389 [doi]
• Flexible and Executable Hardware/Software Interface Modeling for Multiprocessor SoC Design Using SystemCPatrice Gerin, Hao Shen, A. Chureau, Aimen Bouchhima, Ahmed Amine Jerraya. 390-395 [doi]
• A Retargetable Software Timing Analyzer Using Architecture Description LanguageXianfeng Li, Abhik Roychoudhury, Tulika Mitra, Prabhat Mishra, Xu Cheng. 396-401 [doi]
• Automating Logic Rectification by Approximate SPFDsYu-Shen Yang, Subarnarekha Sinha, Andreas G. Veneris, Robert K. Brayton. 402-407 [doi]
• BddCut: Towards Scalable Symbolic Cut EnumerationAndrew C. Ling, Jianwen Zhu, Stephen Dean Brown. 408-413 [doi]
• Node Mergers in the Presence of Don t CaresStephen Plaza, Kai-Hui Chang, Igor L. Markov, Valeria Bertacco. 414-419 [doi]
• Synthesis of Reversible Sequential ElementsMin-Lun Chuang, Chun-Yao Wang. 420-425 [doi]
• Recognition of Fanout-free FunctionsTsung-Lin Lee, Chun-Yao Wang. 426-431 [doi]
• Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologiesGeorges G. E. Gielen. 432-437 [doi]
• Challenges to Accuracy for the Design of Deep-Submicron RF-CMOS CircuitsS. Yoshitomi. 438-441 [doi]
• Advanced tools for simulation and design of oscillators/PLLsXiaolue Lai, Jaijeet S. Roychowdhury. 442-449 [doi]
• A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography EffectsYing Zhou, Zhuo Li, Yuxin Tian, Weiping Shi, Frank Liu. 450-455 [doi]
• Simple and Accurate Models for Capacitance Increment due to Metal Fill InsertionYoungmin Kim, Dusan Petranovic, Dennis Sylvester. 456-461 [doi]
• New Block-Based Statistical Timing Analysis Approaches Without Moment MatchingRuiming Chen, Hai Zhou. 462-467 [doi]
• Parameter Reduction for Variability Analysis by Slice Inverse Regression (SIR) MethodAlexander V. Mitev, Michael Marefat, Dongsheng Ma, Janet Meiling Wang. 468-473 [doi]
• Stochastic Sparse-grid Collocation Algorithm (SSCA) for Periodic Steady-State Analysis of Nonlinear System with Process VariationsJun Tao, Xuan Zeng, Wei Cai, Yangfeng Su, Dian Zhou, Charles Chiang. 474-479 [doi]
• Retiming for Synchronous Data Flow GraphsNikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee. 480-485 [doi]
• Signal-to-Memory Mapping Analysis for Multimedia Signal ProcessingIlie I. Luican, Hongwei Zhu, Florin Balasa. 486-491 [doi]
• MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-ChipT. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan. 492-497 [doi]
• A Run-Time Memory Protection MethodologyUdaya Seshua, Nagaraju Bussa, Bart Vermeulen. 498-503 [doi]
• Short-Circuit Compiler Transformation: Optimizing Conditional BlocksMohammad Ali Ghodrat, Tony Givargis, Alex Nicolau. 504-510 [doi]
• Optimization of Arithmetic Datapaths with Finite Word-Length OperandsSivaram Gopalakrishnan, Priyank Kalla, Florian Enescu. 511-516 [doi]
• Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selectionM. A. Ochoa-Montiel, Bashir M. Al-Hashimi, P. Kollig. 517-522 [doi]
• A Parameterized Architecture Model in High Level Synthesis for Image Processing ApplicationsYazhuo Dong, Yong Dou. 523-528 [doi]
• High-Level Power Estimation and Low-Power Design Space Exploration for FPGAsDeming Chen, Jason Cong, Yiping Fan, Zhiru Zhang. 529-534 [doi]
• Numerical Function Generators Using Edge-Valued Binary Decision DiagramsShinobu Nagayama, Tsutomu Sasao, Jon T. Butler. 535-540 [doi]
• Clock Skew Scheduling with Delay Padding for Prescribed Skew DomainsChuan Lin, Hai Zhou. 541-546 [doi]
• An Efficient Computation of Statistically Critical Sequential Paths Under RetimingMongkol Ekpanyapong, Xin Zhao, Sung Kyu Lim. 547-552 [doi]
• Fast Electrical Correction Using Resizing and BufferingShrirang K. Karandikar, Charles J. Alpert, Mehmet Can Yildiz, Paul Villarrubia, Stephen T. Quay, T. Mahmud. 553-558 [doi]
• SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI designSanghamitra Roy, Charlie Chung-Ping Chen. 559-564 [doi]
• Modeling the Overshooting Effect for CMOS Inverter in Nanometer TechnologiesZhangcai Huang, Hong Yu, Atsushi Kurokawa, Yasuaki Inoue. 565-570 [doi]
• Flow-Through-Queue based Power Management for Gigabit Ethernet ControllerHwisung Jung, Andy Hwang, Massoud Pedram. 571-576 [doi]
• Approximation Algorithm for Process Mapping on Network Processor ArchitecturesChristopher Ostler, Karam S. Chatha, Goran Konjevod. 577-582 [doi]
• Implementation of a Real Time Programmable Encoder for Low Density Parity Check Code on a Reconfigurable Instruction Cell ArchitectureZahid Khan, Tughrul Arslan. 583-588 [doi]
• VLSI Design of Multi Standard Turbo Decoder for 3G and BeyondImran Ahmed, Tughrul Arslan. 589-594 [doi]
• A High-Throughput Low-Power AES Cipher for Network ApplicationsShin-Yi Lin, Chih-Tsun Huang. 595-600 [doi]
• Improving XOR-Dominated Circuits by Exploiting Dependencies between OperandsAjay K. Verma, Paolo Ienne. 601-608 [doi]
• Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design SpaceJianhua Liu, Yi Zhu, Haikun Zhu, Chung-Kuan Cheng, John Lillis. 609-615 [doi]
• An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order OptimizationHaikun Zhu, Yi Zhu, Chung-Kuan Cheng, David M. Harris. 616-621 [doi]
• Optimization of Robust Asynchronous Circuits by Local Input Completeness RelaxationCheoljoo Jeong, Steven M. Nowick. 622-627 [doi]
• Safe Delay Optimization for Physical SynthesisKai-Hui Chang, Igor L. Markov, Valeria Bertacco. 628-633 [doi]
• Overview on Low Power SoC Design TechnologyKimiyoshi Usami. 634-636 [doi]
• Development of Low-power and Real-time VC-1/H.264/MPEG-4 Video Processing HardwareM. Hase, K. Akie, M. Nobori, K. Matsumoto. 637-643 [doi]
• Development of Low Power ISDB-T One-Segment Decoder by Mobile Multi-Media Engine SoC (S1G)K. Mori, M. Suzuki, Y. Ohara, S. Matsuo, A. Asano. 644-648 [doi]
• Low Power Techniques for Mobile Application SoCs Based on Integrated Platform UniPhier Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasaki, Tetsu Hosoki, Masaya Sumita. 649-653 [doi]
• Simultaneous Control of Subthreshold and Gate Leakage Current in Nanometer-Scale CMOS CircuitsYoungsoo Shin, Sewan Heo, Hyung-Ock Kim, Jung Yun Choi. 654-659 [doi]
• Runtime leakage power estimation technique for combinational circuitsYu-Shiang Lin, Dennis Sylvester. 660-665 [doi]
• Logic and Layout Aware Voltage Island Generation for Low Power DesignLiangpeng Guo, Yici Cai, Qiang Zhou, Xianlong Hong. 666-671 [doi]
• A Fast Probability-Based Algorithm for Leakage Current Reduction Considering Controller CostTsung-Yi Wu, Jr-Luen Tzeng, Kuang-Yao Chen. 672-677 [doi]
• A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAsHassan Hassan, Mohab Anis, Mohamed I. Elmasry. 678-683 [doi]
• Approaching Speed-of-light Distortionless Communication for On-chip InterconnectHaikun Zhu, Rui Shi, Chung-Kuan Cheng, Hongyu Chen. 684-689 [doi]
• Delay Uncertainty Reduction by Interconnect and Gate SplittingVineet Agarwal, Jin Sun, Alexander V. Mitev, Janet Meiling Wang. 690-695 [doi]
• Transition Skew Coding: A Power and Area Efficient Encoding Technique for Global On-Chip InterconnectsCharbel J. Akl, Magdy A. Bayoumi. 696-701 [doi]
• Fast Buffered Delay Estimation Considering Process VariationsTien-Ting Fang, Ting-Chi Wang. 702-707 [doi]
• Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip InterconnectArthur Nieuwoudt, Mosin Mondal, Yehia Massoud. 708-713 [doi]
• Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP CoresDan Zhao, Unni Chandran, Hideo Fujiwara. 714-719 [doi]
• Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional BusesFawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara. 720-725 [doi]
• An Architecture for Combined Test Data Compression and Abort-on-Fail TestErik Larsson, Jon Persson. 726-731 [doi]
• RunBasedReordering: A Novel Approach for Test Data Compression and Scan PowerHao Fang, Chenguang Tong, Xu Cheng. 732-737 [doi]
• Systematic Scan ReconfigurationAhmad A. Al-Yamani, Narendra Devta-Prasanna, Arun Gunda. 738-743 [doi]
• Configurable Multi-Processor Platforms for Next Generation Embedded SystemsDavid Goodwin, Chris Rowen, Grant Martin. 744-746 [doi]
• ARM MPCore; The streamlined and scalable ARM11 processor coreKazuyuki Hirata, John Goodacre. 747-748 [doi]
• Nomadik®: A Mobile Multimedia Application Processor PlatformMaurizio Paganini. 749-750 [doi]
• Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk ApproachLe Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong, Sheldon X.-D. Tan. 751-756 [doi]
• Timing-Aware Decoupling Capacitance Allocation in Power Distribution NetworksSanjay Pant, David Blaauw. 757-762 [doi]
• Fast Placement Optimization of Power Supply PadsYu Zhong, Martin D. F. Wong. 763-767 [doi]
• Efficient Second-Order Iterative Methods for IR Drop Analysis in Power GridYu Zhong, Martin D. F. Wong. 768-773 [doi]
• A Current-based Method for Short Circuit Power Calculation under Noisy Input WaveformsHanif Fatemi, Shahin Nazarian, Massoud Pedram. 774-779 [doi]
• Thermal-Aware 3D IC Placement Via TransformationJason Cong, Guojie Luo, Jie Wei, Yan Zhang. 780-785 [doi]
• Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture ProfilingFayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee. 786-791 [doi]
• On Increasing Signal Integrity with Minimal Decap Insertion in Area-Array SoC Floorplan DesignChao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu. 792-797 [doi]
• Voltage Island Generation under Performance Requirement for SoC DesignsWai-Kei Mak, Jr-Wei Chen. 798-803 [doi]
• Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board CodesignRen-Jie Lee, Ming-Fang Lai, Hung-Ming Chen. 804-809 [doi]
• A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited CaptureSeongmoon Wang, Wenlong Wei. 810-816 [doi]
• Warning: Launch off Shift Tests for Delay Faults May Contribute to Test EscapesZhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz. 817-822 [doi]
• AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for Big-D/Small-A Mixed-Signal SoCsSudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar. 823-828 [doi]
• Fault Dictionary Size Reduction for Million-Gate Large CircuitsYu-Ru Hong, Juinn-Dar Huang. 829-834 [doi]
• Cyclic-CPRS : A Diagnosis Technique for BISTed Circuits for Nano-meter TechnologiesChun-Yi Lee, Hung-Mao Lin, Fang-Min Wang, James Chien-Mo Li. 835-840 [doi]
• Preferable Improvements and Changes to FB-DiMM High-Speed Channel for 9.6Gbps OperationAtsushi Hiraishi, Toshio Sugano, Hideki Kusamitsu. 841-845 [doi]
• Xbox360:::TM::: Front Side Bus - A 21.6 GB/s End-to-End Interface DesignDavid W. Siljenberg, Steve Baumgartner, Tim Buchholtz, Mark Maxson, Trevor Timpane, Jeff Johnson. 846-853 [doi]
• Design Consideration of 6.25 Gbps Signaling for High-Performance ServerJian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone. 854-857 [doi]
• System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor; Realizing 3.2 Gbps Data Rate per Memory Lane in Low Cost, High Volume ProductionWai-Yeung Yip, Scott Best, Wendemagegnehu T. Beyene, Ralf Schmitt. 858-865 [doi]
• Flow Time Minimization under Energy ConstraintsJian-Jia Chen, Kazuo Iwama, Tei-Wei Kuo, Hsueh-I Lu. 866-871 [doi]
• Integrating Power Management into Distributed Real-time Systems at Very Low Implementation CostBita Gorjiara, Nader Bagherzadeh, Pai H. Chou. 872-877 [doi]
• A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process VariationMaziar Goudarzi, Tohru Ishihara, Hiroto Yasuura. 878-883 [doi]
• Program Phase Directed Dynamic Cache Way Reconfiguration for Power EfficiencySubhasis Banerjee, G. Surendra, S. K. Nandy. 884-889 [doi]
• CLIPPER: Counter-based Low Impact Processor Power Estimation at Run-timeJorgen Peddersen, Sri Parameswaran. 890-895 [doi]
• Design Methodology for 2.4GHz Dual-Core MicroprocessorNoriyuki Ito, Hiroaki Komatsu, Akira Kanuma, Akihiro Yoshitake, Yoshiyasu Tanamura, Hiroyuki Sugiyama, Ryoichi Yamashita, Ken-ichi Nabeya, Hironobu Yoshino, Hitoshi Yamanaka, Masahiro Yanagida, Yoshitomo Ozeki, Kinya Ishizaka, Takeshi Kono, Yutaka Isoda. 896-901 [doi]
• An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software ToolsFu-Ching Yang, Ing-Jer Huang. 902-907 [doi]
• A Novel Reconfigurable Low Power Distributed Arithmetic Architecture for Multimedia ApplicationsZhenyu Liu, Tughrul Arslan, Ahmet T. Erdogan. 908-913 [doi]
• Exploration of Low Power Adders for a SIMD Data PathGiacomo Paci, Paul Marchal, Luca Benini. 914-919 [doi]
• Micro-architecture Pipelining Optimization with Throughput-Aware FloorplanningYuchun Ma, Zhuoyuan Li, Jason Cong, Xianlong Hong, Glenn Reinman, Sheqin Dong, Qiang Zhou. 920-925 [doi]
• Multithreaded SAT SolvingMatthew D. T. Lewis, Tobias Schubert, Bernd Becker. 926-931 [doi]
• Trace Compaction using SAT-based Reachability AnalysisSean Safarpour, Andreas G. Veneris, Hratch Mangassarian. 932-937 [doi]
• Combinational Equivalence Checking Using Incremental SAT Solving, Output Ordering, and ResetsStefan Disch, Christoph Scholl. 938-943 [doi]
• Fixing Design Errors with Counterexamples and ResynthesisKai-Hui Chang, Igor L. Markov, Valeria Bertacco. 944-949 [doi]