Abstract is missing.
- CausaLearn: Automated Framework for Scalable Streaming-based Causal Bayesian Learning using FPGAsBita Darvish Rouhani, Mohammad GhasemZadeh, Farinaz Koushanfar. 1-10 [doi]
- C-LSTM: Enabling Efficient LSTM using Structured Compression Techniques on FPGAsShuo Wang, Zhe Li 0001, Caiwen Ding, Bo Yuan, Qinru Qiu, Yanzhi Wang, Yun Liang 0001. 11-20 [doi]
- DeltaRNN: A Power-efficient Recurrent Neural Network AcceleratorChang Gao, Daniel Neil, Enea Ceolini, Shih-Chii Liu, Tobi Delbrück. 21-30 [doi]
- A Lightweight YOLOv2: A Binarized CNN with A Parallel Support Vector Regression for an FPGAHiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Shimpei Sato. 31-40 [doi]
- Architecture and Circuit Design of an All-Spintronic FPGAStephen M. Williams, Mingjie Lin. 41-50 [doi]
- Liquid Silicon: A Data-Centric Reconfigurable Architecture Enabled by RRAM TechnologyYue Zha, Jing Li. 51-60 [doi]
- Improving FPGA Performance with a S44 LUT StructureWenyi Feng, Jonathan W. Greene, Alan Mishchenko. 61-66 [doi]
- ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and SchedulingChin Hau Hoo, Akash Kumar 0001. 67-76 [doi]
- Routing Magic: Performing Computations Using Routing Networks and Voting Logic on Unary Encoded DataSoheil Mohajer, Zhiheng Wang 0002, Kia Bazargan. 77-86 [doi]
- A Full-System VM-HDL Co-Simulation Framework for Servers with PCIe-Connected FPGAsShenghsun Cho, Mrunal Patel, Han Chen, Michael Ferdman, Peter Milder. 87-96 [doi]
- Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGAJunzhong Shen, You Huang, Zelong Wang, Yuran Qiao, Mei Wen, Chunyuan Zhang. 97-106 [doi]
- A Customizable Matrix Multiplication Framework for the Intel HARPv2 Xeon+FPGA Platform: A Deep Learning Case StudyDuncan J. M. Moss, Krishnan Srivatsan, Eriko Nurvitadhi, Piotr Ratuszniak, Chris Johnson, Jaewoong Sim, Asit K. Mishra, Debbie Marr, Suchit Subhaschandra, Philip Heng Wai Leong. 107-116 [doi]
- A Framework for Generating High Throughput CNN Implementations on FPGAsHanqing Zeng, Ren Chen, Chi Zhang, Viktor K. Prasanna. 117-126 [doi]
- Dynamically Scheduled High-level SynthesisLana Josipovic, Radhika Ghosal, Paolo Ienne. 127-136 [doi]
- A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT FormulationSteve Dai, Gai Liu, Zhiru Zhang. 137-146 [doi]
- P4-Compatible High-Level Synthesis of Low Latency 100 Gb/s Streaming Packet Parsers in FPGAsJeferson Santiago da Silva, François-Raymond Boyer, J. M. Pierre Langlois. 147-152 [doi]
- Combined Spatial and Temporal Blocking for High-Performance Stencil Computation on FPGAs Using OpenCLHamid Reza Zohouri, Artur Podobas, Satoshi Matsuoka. 153-162 [doi]
- A HOG-based Real-time and Multi-scale Pedestrian Detector Demonstration System on FPGAJan Dürre, Dario Paradzik, Holger Blume. 163-172 [doi]
- Scalable Window Generation for the Intel Broadwell+Arria 10 and High-Bandwidth FPGA SystemsGreg Stitt, Abhay Gupta, Madison N. Emas, David Wilson, Austin Baylis. 173-182 [doi]
- High-Performance QR Decomposition for FPGAsMartin Langhammer, Bogdan Pasca. 183-188 [doi]
- ADAM: Automated Design Analysis and Merging for Speeding up FPGA DevelopmentHo-Cheung Ng, Shuanglong Liu, Wayne Luk. 189-198 [doi]
- Graph-Theoretically Optimal Memory Banking for Stencil-Based Computing KernelsJuan Escobedo, Mingjie Lin. 199-208 [doi]
- Architecture Exploration for HLS-Oriented FPGA Debug OverlaysAl-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton. 209-218 [doi]
- Memory-Efficient Fast Fourier Transform on Streaming Data by Fusing PermutationsFrançois Serre, Markus Püschel. 219-228 [doi]
- Degree-aware Hybrid Graph Traversal on FPGA-HMC PlatformJialiang Zhang, Jing Li. 229-238 [doi]
- Accelerating Graph Analytics by Co-Optimizing Storage and Access on an FPGA-HMC PlatformSoroosh Khoram, Jialiang Zhang, Maxwell Strange, Jing Li. 239-248 [doi]
- Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed ThroughputJakub Cabal, Pavel Benácek, Lukas Kekely, Michal Kekely, Viktor Pus, Jan Korenek. 249-258 [doi]
- FASTCF: FPGA-based Accelerator for STochastic-Gradient-Descent-based Collaborative FilteringShijie Zhou, Rajgopal Kannan, Yu Min, Viktor K. Prasanna. 259-268 [doi]
- Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAsYuan Zhou, Udit Gupta, Steve Dai, Ritchie Zhao, Nitish Kumar Srivastava, Hanchen Jin, Joseph Featherston, Yi-Hsiang Lai, Gai Liu, Gustavo Angarita Velasquez, Wenping Wang, Zhiru Zhang. 269-278 [doi]
- FPGA Fastfood - A High Speed Systolic Implementation of a Large Scale Online Kernel MethodSean Fox, David Boland, Philip Heng Wai Leong. 279-284 [doi]
- Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only)Ruizhe Zhao, Xinyu Niu, Wayne Luk. 285 [doi]
- Continuous Skyline Computation Accelerator with Parallelizing Dominance Relation Calculations: (Abstract Only)Kenichi Koizumi, Kei Hiraki, Mary Inaba. 285 [doi]
- Optimizations of Sequence Alignment on FPGA: A Case Study of Extended Sequence Alignment (Abstact Only)Zheming Jin, Kazutomo Yoshii. 285 [doi]
- FastTrack: Exploiting Fast FPGA Wiring for Implementing NoC Shortcuts (Abstract Only)Nachiket Kapre, Tushar Krishna. 286 [doi]
- A FPGA Friendly Approximate Computing Framework with Hybrid Neural Networks: (Abstract Only)Haiyue Song, Xiang Song, Tianjian Li, Hao Dong, Naifeng Jing, Xiaoyao Liang, Li Jiang. 286 [doi]
- An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only)Yuze Chi, Peipei Zhou, Jason Cong. 286 [doi]
- Evaluation of OpenCL Performance-oriented Optimizations for Streaming Kernels on the FPGA: (Abstract Only)Zheming Jin, Hal Finkel. 287 [doi]
- In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only)Eriko Nurvitadhi, Jeffrey J. Cook, Asit K. Mishra, Debbie Marr, Kevin Nealis, Philip Colangelo, Andrew C. Ling, Davor Capalija, Utku Aydonat, Sergey Shumarayev, Aravind Dasu. 287 [doi]
- K-Flow: A Programming and Scheduling Framework to Optimize Dataflow Execution on CPU-FPGA Platforms: (Abstract Only)Jason Cong, Zhenman Fang, Yao Hu, Di Wu 0010. 287 [doi]
- FPGA-based LSTM Acceleration for Real-Time EEG Signal Processing: (Abstract Only)Zhe Chen, Andrew Howe, Hugh T. Blair, Jason Cong. 288 [doi]
- Understanding Performance Differences of FPGAs and GPUs: (Abtract Only)Jason Cong, Zhenman Fang, Michael Lo, HanRui Wang, Jingxian Xu, Shaochong Zhang. 288 [doi]
- Solving Satisfiability Problem on Quantum Annealer: A Lesson from FPGA CAD Tools: (Abstract Only)Juexiao Su, Lei He. 289 [doi]
- Towards Serial-Equivalent Parallel Routing for FPGAs: (Abstract Only)Minghua Shen, Wentai Zhang, Nong Xiao, Guojie Luo. 289 [doi]
- Domino: An Asynchronous and Energy-efficient Accelerator for Graph Processing: (Abstract Only)Chongchong Xu, Chao Wang, YiWei Zhang, Lei Gong, Xi Li, Xuehai Zhou. 289 [doi]
- Software/Hardware Co-design for Multichannel Scheduling in IEEE 802.11p MLME: (Abstract Only)Nan Ding, Wei Zhang, Yanhua Ma, Zhenguo Gao. 289 [doi]
- DATuner: An Extensible Distributed Autotuning Framework for FPGA Design and Design Automation: (Abstract Only)Gai Liu, Ecenur Ustun, Shaojie Xiang, Chang Xu, Guojie Luo, Zhiru Zhang. 290 [doi]
- Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only)Matej Bartík, Sven Ubik, Pavel Kubalík, Tomás Benes. 290 [doi]
- BoxPlacer: Force Directed-Based Timing-Driven Placement for Large-Scale FPGAs: (Abstract Only)Minghua Shen, Jiaxi Zhang, Nong Xiao, Guojie Luo. 290 [doi]
- Design of an MTJ-Based Nonvolatile LUT Circuit with a Data-Update Minimized Shift Operation for an Ultra-Low-Power FPGA: (Abstract Only)Daisuke Suzuki, Takahiro Hanyu. 291 [doi]
- Software-Defined FPGA-Based Accelerator for Deep Convolutional Neural Networks: (Abstract Only)Yankang Du, Qinrang Liu, Shuai Wei, Chen Gao. 291 [doi]
- Mapping Large-Scale DNNs on Asymmetric FPGAs: (Abstract Only)Wentai Zhang, Jiaxi Zhang, Minghua Shen, Nong Xiao, Guojie Luo. 291 [doi]
- High-Throughput Lossless Compression on Tightly Coupled CPU-FPGA Platforms: (Abstract Only)Weikang Qiao, Jieqiong Du, Zhenman Fang, Libo Wang, Michael Lo, Mau-Chung Frank Chang, Jason Cong. 291 [doi]
- HexCell: a Hexagonal Cell for Evolvable Systolic Arrays on FPGAs: (Abstract Only)Fady Hussein, Luka Daoud, Nader Rafla. 293 [doi]
- A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract OnlyShuanglong Liu, Xinyu Niu, Wayne Luk. 293 [doi]
- Performance Comparison of Multiples and Target Detection with Imager-driven Processing Mode for Ultrafast-Imager: (Abstract Only)Xiaoyu Yu, Dong Ye. 293 [doi]
- SIFT Keypoint Descriptor Matching Algorithm: A Fully Pipelined Accelerator on FPGA(Abstract Only)Luka Daoud, Muhammad Kamran Latif, Nader Rafla. 294 [doi]
- 5)(Abstract Only)Mikhail Asiatici, Damian Maiorano, Paolo Ienne. 294 [doi]
- FGC: A Tool-flow for Generating and Configuring Custom FPGAs(Abstract Only)Oluseyi A. Ayorinde, He Qi, Benton H. Calhoun. 294 [doi]
- Exploration of Low Numeric Precision Deep Learning Inference Using Intel® FPGAs: (Abstract Only)Philip Colangelo, Nasibeh Nasiri, Eriko Nurvitadhi, Asit K. Mishra, Martin Margala, Kevin Nealis. 294 [doi]
- A Self-adaptation Method of Fitting Convolutional Neural Network into FPGA: Abstract Only)Ning Mao, Zhihong Huang, Xing Wei, He Zhao, Xinkai Di, Le Yu, Haigang Yang. 295 [doi]
- LEOSoC: An Open-Source Cross-Platform Embedded Linux Library for Managing Hardware Accelerators in Heterogeneous System-on-Chips(Abstract Only)Andrea Guerrieri, Sahand Kashani-Akhavan, Mikhail Asiatici, Pasquale Lombardi, Bilel Belhadj, Paolo Ienne. 295 [doi]