Table of Contents

• A high linearity compact timing vernier for CMOS timing generatorJun Kohno, Tatsuro Akiyama, Dai Kato, Makoto Imamura. 1-8 [doi]
• Automated test program generation for automotive devicesAnke Drappa, Peter Huber, Jon Vollmar. 1-10 [doi]
• Complete testing of receiver jitter toleranceTimothy Daniel Lyons. 9-18 [doi]
• New tools and methodology for advanced parametric and defect structure testRaphael Robertazzi, Louis Medina, Ernesto Shiling, Garry Moore, Ronald Geiger, Jiun-Hsin Liao, John Williamson. 19-28 [doi]
• A low-cost ATE phase signal generation technique for test applicationsSadok Aouini, Kun Chuai, Gordon W. Roberts. 29-38 [doi]
• The scan-DFT features of AMD's next-generation microprocessor coreMahmut Yilmaz, Baosheng Wang, Jayalakshmi Rajaraman, Tom Olsen, Kanwaldeep Sobti, Dwight Elvey, Jeff Fitzgerald, Grady Giles, Wei-Yu Chen. 39-48 [doi]
• Testing the IBM Power 7™ 4 GHz eight core microprocessorJames Crafts, David Bogdan, Dennis Conti, Donato O. Forlenza, Orazio P. Forlenza, William V. Huott, Mary P. Kusko, Edward Seymour, Timothy Taylor, Brian Walsh. 49-58 [doi]
• Optimization of burn-in test for many-core processors through adaptive spatiotemporal power migrationMinki Cho, Nikhil Sathe, Arijit Raychowdhury, Saibal Mukhopadhyay. 59-68 [doi]
• Redundant core testing on the cell BE microprocessorDavid Iverson, Dan Dickinson, John Masson, Christina Newman-LaBounty, Daniel Simmons, William Tanona. 68-73 [doi]
• BIST of I/O circuit parameters via standard boundary scanStephen K. Sunter, Matthias Tilmann. 74-83 [doi]
• Clock Gate Test PointsNarendra Devta-Prasanna, Arun Gunda. 84-93 [doi]
• Design and test of latch-based circuits to maximize performance, yield, and delay test qualityKun Young Chung, Sandeep K. Gupta. 94-103 [doi]
• Testing of latch based embedded arrays using scan testsFan Yang, Sreejit Chakravarty. 104-113 [doi]
• Clock control architecture and ATPG for reducing pattern count in SoC designs with multiple clock domainsTom Waayers, Richard Morren, Xijiang Lin, Mark Kassab. 114-123 [doi]
• Towards effective and compression-friendly test of memory interface logicV. R. Devanathan, Alan Hales, Sumant Kale, Dharmesh Sonkar. 124-133 [doi]
• Test cycle power optimization for scan-based designsKun-Han Tsai, Yu Huang 0005, Wu-Tung Cheng, Ting-Pu Tai, Augusli Kifli. 134-143 [doi]
• Automated trace signals selection using the RTL descriptionsHo Fai Ko, Nicola Nicolici. 144-153 [doi]
• QED: Quick Error Detection tests for effective post-silicon validationTed Hong, Yanjing Li, Sung-Boem Park, Diana Mui, David Lin, Ziyad Abdel Kaleq, Nagib Hakim, Helia Naeimi, Donald S. Gardner, Subhasish Mitra. 154-163 [doi]
• A kernel-based approach for functional test program generationPo-Hsien Chang, Li-C. Wang, Jayanta Bhadra. 164-173 [doi]
• Modeling TSV open defects in 3D-stacked DRAMLi Jiang, Yuxi Liu, Lian Duan, Yuan Xie, Qiang Xu. 174-182 [doi]
• On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICsMottaqiallah Taouil, Said Hamdioui, Jouke Verbree, Erik Jan Marinissen. 183-192 [doi]
• Optimization methods for post-bond die-internal/external testing in 3D stacked ICsBrandon Noia, Krishnendu Chakrabarty, Erik Jan Marinissen. 193-201 [doi]
• Error-locality-aware linear coding to correct multi-bit upsets in SRAMsSaeed Shamshiri, Kwang-Ting Cheng. 202-211 [doi]
• Post-manufacturing ECC customization based on Orthogonal Latin Square codes and its application to ultra-low power cachesRudrajit Datta, Nur A. Touba. 212-218 [doi]
• Shadow checker (SC): A low-cost hardware scheme for online detection of faults in small memory structures of a microprocessorRance Rodrigues, Sandip Kundu, Omer Khan. 219-228 [doi]
• Evaluation techniques of frequency-dependent I/Q imbalances in wideband quadrature mixersKoji Asami, Toshiaki Kurihara, Yushi Inada. 229-236 [doi]
• Synthetic DSP approach for novel FPGA-based measurement of error vector magnitudeDevin Morris, William R. Eisenstadt, Andrea Paganini, Mustapha Slamani, Timothy Platt, John Ferrario. 237-244 [doi]
• Post-production performance calibration in analog/RF devicesNathan Kupp, He Huang, Petros Drineas, Yiorgos Makris. 245-254 [doi]
• Increasing PRPG-based compression by delayed justificationPeter Wohl, John A. Waicukauski, T. Finklea. 255-264 [doi]
• Dynamic channel allocation for higher EDT compression in SoC designsMark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer. 265-274 [doi]
• Predictive analysis for projecting test compression levelsOzgur Sinanoglu, Sobeeh Almukhaizim. 275-284 [doi]
• Defect-oriented cell-internal testingFriedrich Hapke, Wilfried Redemund, Jürgen Schlöffel, Rene Krenz-Baath, Andreas Glowatz, Michael Wittke, Hamidreza Hashempour, Stefan Eichenberger. 285-294 [doi]
• Modeling the impact of process variation on resistive bridge defectsS. Saqib Khursheed, Shida Zhong, Robert C. Aitken, Bashir M. Al-Hashimi, Sandip Kundu. 295-304 [doi]
• Automatic classification of bridge defectsJeffrey E. Nelson, Wing Chiu Tam, Ronald D. Blanton. 305-314 [doi]
• A high density small size RF test module for high throughput multiple resource testingM. Kimishima, S. Mizuno, T. Seki, H. Takeuti, H. Nagami, H. Shirasu, Y. Haraguti, J. Okayasu, M. Nakanishi. 315-324 [doi]
• RADPro: Automatic RF analyzer and diagnostic program generation toolSukeshwar Kannan, Bruce C. Kim, Ganesh Srinivasan, Friedrich Taenzlar, Richard Antley, Craig Force, Falah Mohammed. 325-333 [doi]
• Timing skew compensation technique using digital filter with novel linear phase conditionKoji Asami, Hiroyuki Miyajima, Tsuyoshi Kurosawa, Takenori Tateiwa, Haruo Kobayashi. 334-342 [doi]
• nGFSIM : A GPU-based fault simulator for 1-to-n detection and its applicationsHuawei Li, Dawen Xu, Yinhe Han, Kwang-Ting Cheng, Xiaowei Li 0001. 343-352 [doi]
• Highly efficient parallel ATPG based on shared memoryX. Cai, Peter Wohl, John A. Waicukauski, Pramod Notiyath. 353-359 [doi]
• A diagnostic test generation systemYu Zhang, Vishwani D. Agrawal. 360-368 [doi]
• Mask versus Schematic - an enhanced design-verification flow for first silicon successTseng-Chin Luo, Eric Leong, Mango Chia-Tso Chao, Philip A. Fisher, Wen-Hsiang Chang. 369-377 [doi]
• Systematic defect identification through layout snippet clusteringWing Chiu Tam, Osei Poku, Ronald D. Blanton. 378-387 [doi]
• Hard to find, easy to find systematics; just find themRao Desineni, Leah Pastel, Maroun Kassab, Robert Redburn. 388-397 [doi]
• Structural approach for built-in tests in RF devicesDeepa Mannath, Dallas Webster, Victor Montaño-Martinez, David Cohen, Shai Kush, Ganesan Thiagarajan, Adesh Sontakke. 398-404 [doi]
• Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recoverySudeep Puligundla, Fulvio Spagna, Lidong Chen, Amanda Tran. 405-409 [doi]
• Experiences with parametric BIST for production testing PLLs with picosecond precisionRakesh Kinger, Swetha Narasimhawsamy, Stephen K. Sunter. 410-418 [doi]
• ADC linearity testing method with single analog monitoring portTomohiro Kawachi, Koichi Irie. 419-426 [doi]
• Fault models and test methods for subthreshold SRAMsChen-Wei Lin, Hung-Hsin Chen, Hao-Yu Yang, Mango Chia-Tso Chao, Rei-Fu Huang. 427-436 [doi]
• Detecting memory faults in the presence of bit line coupling in SRAM devicesSandra Irobi, Zaid Al-Ars, Said Hamdioui. 437-446 [doi]
• A programmable BIST for DRAM testing and diagnosisPaolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, Y. Zhang. 447-456 [doi]
• Rapid FPGA delay characterization using clock synthesis and sparse samplingMehrdad Majzoobi, Eva L. Dyer, Ahmed Elnably, Farinaz Koushanfar. 457-466 [doi]
• Principal Component Analysis-based compensation for measurement errors due to mechanical misalignments in PCB testingXin He, Yashwant K. Malaiya, Anura P. Jayasumana, Kenneth P. Parker, Stephen Hird. 467-476 [doi]
• Improving fault diagnosis accuracy by automatic test set modificationLuca Amati, Cristiana Bolchini, Fabio Salice, Federico Franzoso. 477-484 [doi]
• Board-level fault diagnosis using an error-flow dictionaryZhaobo Zhang, Zhanglei Wang, Xinli Gu, Krishnendu Chakrabarty. 485-494 [doi]
• Characterizing mechanical performance of Board Level Interconnects for In-Circuit TestRosa D. Reinosa, Aileen Allen, Elizabeth Benedetto, Alan Mcallister. 495-505 [doi]
• STIL P1450.4: A standard for test flow specificationJim O'Reilly, Ajay Khoche, Ernst Wahl, Bruce R. Parnas. 506-515 [doi]
• Concurrent test planningBethany Van Wagenen, Edward Seng. 516-525 [doi]
• Lessons from at-speed scan deployment on an Intel® Itanium® microprocessorPankaj Pant, Joshua Zelman, Glenn Colón-Bonet, Jennifer Flint, Steve Yurash. 526-535 [doi]
• Path coverage based functional test generation for processor marginality validationSuriyaprakash Natarajan, Arun Krishnamachary, Eli Chiprout, Rajesh Galivanche. 544-552 [doi]
• Mining AC delay measurements for understanding speed-limiting pathsJanine Chen, Brendon Bolin, Li-C. Wang, Jing Zeng, Dragoljub Gagi Drmanac, Michael Mateja. 553-562 [doi]
• Solutions for undetected shorts on IEEE 1149.1 self-monitoring pinsC. J. Clark, Dave Dubberke, Kenneth P. Parker, Bill Tuthill. 563-570 [doi]
• Surviving state disruptions caused by test: The "Lobotomy Problem"Kenneth P. Parker. 571-578 [doi]
• Commanded Test Access Port operationsLee Whetsel. 579-588 [doi]
• Precision audio nulling instrumentation achieves near -140dB measurements in a production environmentCarl Karandjeff, Chris Hannaford. 589-598 [doi]
• Practical active compensation techniques for ATE power supply response for testing of mixed signal data storage SOCsSuri Basharapandiyan, Yi Cai. 599-605 [doi]
• Package test interface fixture considering low cost solution, high electrical performance, and compatibility with fine pitch packagesKi-Jae Song, Hunkyo Seo, Sang-hyun Ko. 606-614 [doi]
• Constrained ATPG for functional RTL circuits using F-ScanMarie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara. 615-624 [doi]
• RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverageAlodeep Sanyal, Krishnendu Chakrabarty, Mahmut Yilmaz, Hideo Fujiwara. 625-634 [doi]
• A fast and highly accurate path delay emulation framework for logic-emulation of timing speculationShuou Nomura, Karthikeyan Sankaralingam, Ranganathan Sankaralingam. 635-644 [doi]
• Leveraging existing power control circuits and power delivery architecture for variability measurementDhruva Acharyya, Kanak Agarwal, Jim Plusquellic. 645-653 [doi]
• An on-line monitoring technique for electrode degradation in bio-fluidic microsystemsQais Al-Gayem, Hongyuan Liu, Andrew Richardson, Nick Burd, M. Kumar. 654-663 [doi]
• Estimating defect-type distributions through volume diagnosis and defect behavior attributionXiaochun Yu, Ronald D. Blanton. 664-673 [doi]
• Adaptive test flow for mixed-signal/RF circuits using learned information from device under testEnder Yilmaz, Sule Ozev, Kenneth M. Butler. 674-683 [doi]
• Analog neural network design for RF built-in self-testDzmitry Maliuk, Haralampos-G. D. Stratigopoulos, He Huang, Yiorgos Makris. 684-693 [doi]
• A new method for estimating spectral performance of ADC from INLJingbo Duan, Le Jin, Degang Chen. 694-703 [doi]
• Low power compression of incompatible test cubesDariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, P. Szczerbicki, Jerzy Tyszer. 704-713 [doi]
• Low capture power at-speed test in EDT environmentElham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab. 714-723 [doi]
• Low cost at-speed testing using On-Product Clock Generation compatible with test compressionBrion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, R. Malneedi, Thomas J. Snethen, Vikram Iyengar, David E. Lackey, Gary Grise. 724-733 [doi]
• MT-SBST: Self-test optimization in multithreaded multicore architecturesNikos Foutris, Mihalis Psarakis, Dimitris Gizopoulos, Andreas Apostolakis, Xavier Vera, Antonio González. 734-743 [doi]
• On techniques for handling soft errors in digital circuitsWarin Sootkaneung, Kewal K. Saluja. 744-752 [doi]
• Soft error reliability aware placement and routing for FPGAsMohammed A. Abdul-Aziz, Mehdi Baradaran Tahoori. 753-761 [doi]
• AXIe®: Open architecture test system standardAl Czamara. 801 [doi]
• AXIe® 2.0 and MVP-C: Open ATE software standardsKenneth Spargo. 802 [doi]
• A novel approach to improve test coverage of BSR cellsAnkush Srivastava, Ajay Prajapati, Vinay Soni. 803 [doi]
• A MEMS based device interface boardNabeeh Kandalaft, Iftekhar Ibne Basith, Rashid Rashidzadeh. 804 [doi]
• Is test power reduction through X-filling good enough?Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed. 805 [doi]
• A tester architecture suitable for MEMS calibration and testingLyl M. Ciganda Brasca, Paolo Bernardi, Matteo Sonza Reorda, Dimitri Barbieri, Maurizio Straiotto, Luciano Bonaria. 806 [doi]
• The AB-filling methodology for power-aware at-speed scan testingTsung-Tang Chen, Po-Han Wu, Kung-Han Chen, Jiann-Chyi Rau, Shih-Ming Tzeng. 807 [doi]
• Scan chain securization though Open-Circuit DeadlocksMichele Portolan, Bradford G. Van Treuren, Suresh Goyal. 808 [doi]
• Using context based methods for test data compressionSara Karamati, Zainalabedin Navabi. 809 [doi]
• A roaming memory test bench for detecting particle induced SEUsJean Marc Gallière, Paolo Rech, Patrick Girard, Luigi Dilillo. 810 [doi]
• Detecting and diagnosing open defectsDat Tran, LeRoy Winemberg, Darrell Carder, Xijiang Lin, Joe LeBritton, Bruce Swanson. 811 [doi]
• DFM aware bridge pair extraction for manufacturing test developmentSarveswara Tammali, Vishal Khatri, Gowrysankar Shanmugam, Mark Terry. 812 [doi]
• Methodology for early and accurate test power estimation at RTLAbhay Singh, Milan Shetty, Srivaths Ravi, Ravindra Nibandhe. 813 [doi]
• A practical scan re-use scheme for system testKelly Lee. 814 [doi]
• Mutation-based diagnostic test generation for hardware design error diagnosisShujun Deng, Kwang-Ting Cheng, Jinian Bian, Zhiqiu Kong. 815 [doi]
• On generation of a universal path candidate set containing testable long pathsZijian He, Tao Lv, Huawei Li, Xiaowei Li 0001. 816 [doi]
• System reliability evaluation using concurrent multi-level simulation of structural faultsMichael A. Kochte, Christian G. Zoellin, Rafal Baranowski, Michael E. Imhof, Hans-Joachim Wunderlich, Nadereh Hatami, Stefano Di Carlo, Paolo Prinetto. 817 [doi]
• Case study of scan chain diagnosis and PFA on a low yield waferYu Huang 0005, Brady Benware, Wu-Tung Cheng, Ting-Pu Tai, Feng-Ming Kuo, Yuan-Shih Chen. 818 [doi]
• Vendor-agnostic native compression engineVance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday. 819 [doi]
• Parity prediction synthesis for nano-electronic gate designsD. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich. 820 [doi]
• Multiple fault activation cycle tests for transistor stuck-open faultsNarendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz. 821 [doi]