Abstract is missing.
- The Evolving Role of Test ... it is now a Value Add OperationPhil Nigh. 3-3 [doi]
- Using TMR Architectures for Yield ImprovementJulien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. 7-15 [doi]
- Module Grouping for Defect Tolerance in Nanoscale MemoryYoonjae Huh, Yoon-Hwa Choi. 16-23 [doi]
- Coping with Obsolescence of Processor Cores in Critical ApplicationsFrancesco Abate, Massimo Violante. 24-32 [doi]
- A Low-Power Safety Mode for Variation Tolerant Systems-on-ChipDavid Wolpert, Paul Ampadu. 33-41 [doi]
- Built-in-Self-Diagnostics for a NoC-Based Reconfigurable IC for Dependable Beamforming ApplicationsOscar Kuiken, Xiao Zhang, Hans G. Kerkhoff. 45-53 [doi]
- Network Fault Model for Dependability Assessment of Networked Embedded SystemsFranco Fummi, Davide Quaglia, Francesco Stefanni. 54-62 [doi]
- Obtaining Microprocessor Vulnerability Factor Using Formal MethodsSyed Z. Shazli, Mehdi Baradaran Tahoori. 63-71 [doi]
- System Reliabilities When Using Triple Modular Redundancy in Quantum-Dot Cellular AutomataTimothy J. Dysart, Peter M. Kogge. 72-80 [doi]
- Error Detection and Tolerance for Scaled Electronic TechnologiesKartik Mohanram. 83-83 [doi]
- Hardware Trojan Detection and Isolation Using Current Integration and Localized Current AnalysisXiaoxiao Wang, Hassan Salmani, Mohammad Tehranipoor, James F. Plusquellic. 87-95 [doi]
- Built-In Proactive Tuning System for Circuit Aging ResilienceNimay Shah, Rupak Samanta, Ming Zhang, Jiang Hu, Duncan Walker. 96-104 [doi]
- Exploring Density-Reliability Tradeoffs on Nanoscale Substrates: When do smaller less reliable devices make sense?Andrey V. Zykov, Gustavo de Veciana. 105-113 [doi]
- Impact of Technology and Voltage Scaling on the Soft Error Susceptibility in Nanoscale CMOSVikas Chandra, Robert C. Aitken. 114-122 [doi]
- Enhancing Silicon Debug via Periodic MonitoringJoon-Sung Yang, Nur A. Touba. 125-133 [doi]
- A Digital BIST for Phase-Locked LoopsKevin Sliech, Martin Margala. 134-142 [doi]
- On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan DesignsShianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte. 143-151 [doi]
- Analyzing the Impact of Fault Tolerant BIST for VLSI DesignSaurabh Jain, W. Robert Daasch, David Armbrust. 152-160 [doi]
- Targeting Zero DPPM - Can we ever get there?Nilanjan Mukherjee. 163-163 [doi]
- A BIST Technique for Crosstalk Noise Detection in FPGAsWaleed K. Al-Assadi, Sindhu Kakarla. 167-175 [doi]
- A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate NetworksManoj Kumar Goparaju, Ashok Kumar Palaniswany, Spyros Tragoudas. 176-183 [doi]
- A Framework to Evaluate the Trade-off among AVF Performance and Area of Soft Error Tolerant MicroprocessorsRui Gong, Kui Dai, Zhiying Wang. 184-192 [doi]
- A Power Efficient Masking Technique for Design of Robust Embedded Systems against SEUs and SETMahdi Fazeli, Seyed Ghassem Miremadi. 193-201 [doi]
- Can Knowledge Regarding the Presence of Countermeasures Against Fault Attacks Simplify Power Attacks on Cryptographic Devices?Francesco Regazzoni, Thomas Eisenbarth, Luca Breveglieri, Paolo Ienne, Israel Koren. 202-210 [doi]
- Modeling and Evaluation of Threshold Defect ToleranceZachary D. Patitz, Nohpill Park. 211-219 [doi]
- Defect Tolerance for a Capacitance Based Nanoscale BiosensorGlenn H. Chapman, Vijay K. Jain. 220-228 [doi]
- Fault Detection of Bloom Filters for Defect MapsJae Young Choi, Yoon-Hwa Choi. 229-235 [doi]
- Fault Tolerant Schemes for QCA SystemsXiaojun Ma, Fabrizio Lombardi. 236-244 [doi]
- On Reducing Circuit Malfunctions Caused by Soft ErrorsIlia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker. 245-253 [doi]
- Realization of L2 Cache Defect Tolerance Using Multi-bit ECCHongbin Sun, Nanning Zheng, Tong Zhang. 254-262 [doi]
- Selective Hardening of NanoPLA CircuitsIlia Polian, Wenjing Rao. 263-271 [doi]
- Soft Error Hardened FF Capable of Detecting Wide Error PulseShuangyu Ruan, Kazuteru Namba, Hideo Ito. 272-280 [doi]
- XOR-based Low Cost Checkers for Combinational LogicCarlos Arthur Lang Lisbôa, Luigi Carro. 281-289 [doi]
- Minimization of CTS of k-CNOT Circuits for SSF and MSF ModelMuhammad Ibrahim, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu. 290-298 [doi]
- Architectural Vulnerability Factor (or, does a soft error matter?)Shubu Mukherjee. 301-301 [doi]
- Automatic Detection of In-field eld Defect Growth in Image SensorsJenny Leung, Glenn H. Chapman, Israel Koren, Zahava Koren. 305-313 [doi]
- Material Fatigue and Reliability of MEMS AccelerometersXingguo Xiong, Yu-Liang Wu, Wen-Ben Jone. 314-322 [doi]
- Fault-Tolerance with Graceful Degradation in Quality: A Design Methodology and Its Application to Digital Signal Processing SystemsNilanjan Banerjee, Charles Augustine, Kaushik Roy. 323-331 [doi]
- Design Space Exploration for the Design of ReliableCristiana Bolchini, Antonio Miele. 332-340 [doi]
- A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic CircuitAbhisek Pan, James W. Tschanz, Sandip Kundu. 343-351 [doi]
- Adaptive Error Control for NoC Switch-to-Switch Links in a Variable Noise EnvironmentQiaoyan Yu, Paul Ampadu. 352-360 [doi]
- Arbitrary Error Detection in Combinational Circuits by Using PartitioningOsnat Keren, Ilya Levin, Vladimir Ostrovsky, Beni Abramov. 361-369 [doi]
- Error Detect Logic Resulting in Faster Address Generate and Decode for CachesPrashant D. Joshi. 370-377 [doi]
- A Case Study of ATPG Delay Path Performance Based on Measured Power Rail IntegrityZahi S. Abuhamdeh. 381-381 [doi]
- ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume ReductionSantiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz. 385-393 [doi]
- Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan CellsFan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz. 394-402 [doi]
- Efficient Determination of Fault Criticality for Manufacturing Test Set OptimizationYiwen Shi, Kellie DiPalma, Jennifer Dworak. 403-411 [doi]
- Core Test Wrapper Design to Reduce Test Application Time for Modular SoC TestingHyunbean Yi, Sandip Kundu. 412-420 [doi]
- Computing at the NanoscaleJohn E. Savage. 423-423 [doi]
- A Generalized Approach for the Use of Convolutional Coding in SEU MitigationLaura Frigerio, Matteo A. Radaelli, Fabio Salice. 427-435 [doi]
- A Novel Error Detection and Correction Technique for RNS Based FIR FiltersSalvatore Pontarelli, Gian-Carlo Cardarilli, Marco Re, Adelio Salsano. 436-444 [doi]
- An Asymmetric Checkpointing and Rollback Error Recovery Scheme for Embedded ProcessorsHamed Tabkhi, Seyed Ghassem Miremadi, Alireza Ejlali. 445-453 [doi]
- Design and Evaluation of a Timestamp-Based Concurrent Error Detection Method (CED) in a Modern Microprocessor ControllerMichail Maniatakos, Naghmeh Karimi, Yiorgos Makris, Abhijit Jas, Chandra Tirumurti. 454-462 [doi]
- Novel On-Chip Clock Jitter Measurement Scheme for High Performance MicroprocessorsCecilia Metra, Martin Omaña, T. M. Mak, Asifur Rahman, Simon Tam. 465-473 [doi]
- Prioritization of Paths for DiagnosisRajsekhar Adapa, Spyros Tragoudas. 474-481 [doi]
- Delay Fault Testability on Two-Rail Logic CircuitsKazuteru Namba, Hideo Ito. 482-490 [doi]
- Diagnosis of Analog Circuits by Using Multiple Transistors and Data SamplingYukiya Miura, Jiro Kato. 491-499 [doi]
- Design for Test Challenges of High Performance/Low Power MicroprocessorsKamran Zarrineh. 503-503 [doi]
- Defect-Tolerant Hybrid CMOS/Nanoelectronic CircuitsKonstantin Likharev. 504-504 [doi]
- A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access MemoryYoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi. 507-515 [doi]
- A Tile-Based Error Model for Forward Growth of DNA Self-AssemblyMasoud Hashempour, Zahra Mashreghian Arani, Fabrizio Lombardi. 516-524 [doi]
- Checkpointing of Rectilinear Growth in DNA Self-AssemblyStephen Frechette, Yong-Bin Kim, Fabrizio Lombardi. 525-533 [doi]
- Fabrication Variations and Defect Tolerance for Nanomagnet-Based QCAMichael Nemier, Michael Crocker, Xiaobo Sharon Hu. 534-542 [doi]