Manoj Kumar Goparaju, Ashok Kumar Palaniswany, Spyros Tragoudas. A Fault Tolerance Aware Synthesis Methodology for Threshold Logic Gate Networks. In Cristiana Bolchini, Yong-Bin Kim, Dimitris Gizopoulos, Mohammad Tehranipoor, editors, 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA. pages 176-183, IEEE Computer Society, 2008. [doi]
Abstract is missing.