Table of Contents

• Test generator with preselected toggling for low power built-in self-testJanusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie. 1-6 [doi]
• A Built-In Self-Test scheme for DDR memory output timing test and measurementHyunjin Kim, Jacob A. Abraham. 7-12 [doi]
• HBIST: An approach towards zero external test costMayur Bubna, Kaushik Roy, Ashish Goel. 13-18 [doi]
• Smart selection of indirect parameters for DC-based alternate RF IC testingHaithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma. 19-24 [doi]
• Analog/RF test ordering in the early stages of production testingNourredine Akkouche, Salvador Mir, Emmanuel Simeu, Mustapha Slamani. 25-30 [doi]
• A SAR ADC missing-decision level detection and removal techniqueJiun-Lang Huang, X.-L. Huang, Yung-Fa Chou, Ding-Ming Kwai. 31-36 [doi]
• Self-adaptive power gating with test circuit for on-line characterization of energy inflection activityAmit Ranjan Trivedi, Saibal Mukhopadhyay. 38-43 [doi]
• Comprehensive online defect diagnosis in on-chip networksAmirali Ghofrani, Ritesh Parikh, Saeed Shamshiri, Andrew DeOrio, Kwang-Ting Cheng, Valeria Bertacco. 44-49 [doi]
• A pseudo-dynamic comparator for error detection in fault tolerant architecturesD. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich. 50-55 [doi]
• Built-in-Self Test of transmitter I/Q mismatch using self-mixing envelope detectorAfsaneh Nassery, Srinath Byregowda, Sule Ozev, Marian Verhelst, Mustapha Slamani. 56-61 [doi]
• Towards a fully stand-alone analog/RF BIST: A cost-effective implementation of a neural classifierDzmitry Maliuk, Nathan Kupp, Yiorgos Makris. 62-67 [doi]
• An on-chip NBTI monitor for estimating analog circuit degradationSyed Askari, Mehrdad Nourani, Mini Rawat. 68-73 [doi]
• An oscillation-based test structure for timing information extractionEun-jung Jang, Anne Gattiker, Sani R. Nassif, Jacob A. Abraham. 74-79 [doi]
• Silicon evaluation of faster than at-speed transition delay testsSreejit Chakravarty, Narendra Devta-Prasanna, Arun Gunda, Junxia Ma, Fan Yang, H. Guo, R. Lai, D. Li. 80-85 [doi]
• A Bayesian-based process parameter estimation using IDDQ current signatureMichihiro Shintani, Takashi Sato. 86-91 [doi]
• Direct connection and testing of TSV and microbump devices using NanoPierce™ contactor for 3D-IC integrationOnnik Yaglioglu, Ben Eldridge. 96-101 [doi]
• Test cost optimization technique for the pre-bond test of 3D ICsYong-Xiao Chen, Yu-Jen Huang, Jin-Fu Li. 102-107 [doi]
• Cost modeling and analysis for interposer-based three-dimensional ICYing-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu. 108-113 [doi]
• Delay test resource allocation and scheduling for multiple frequency domainsBaris Arslan, Alex Orailoglu. 114-119 [doi]
• Detection of gate-oxide defects with timing tests at reduced power supplyXi Qian, Chao Han, Adit D. Singh. 120-126 [doi]
• Small-delay defects detection under process variation using Inter-Path CorrelationFrancisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu. 127-132 [doi]
• Test of phase interpolators in high speed I/Os using a sliding window searchJi Hwan (Paul) Chun, Siew Mooi Lim, Shao Chee Ong, Jae-Wook Lee, Jacob A. Abraham. 134-139 [doi]
• Dual-frequency incoherent subsampling driven test response acquisition of spectrally sparse wideband signals with enhanced time resolutionNicholas Tzou, Thomas Moon, Xian Wang, Hyun Woo Choi, Abhijit Chatterjee. 140-145 [doi]
• Low-cost high-speed pseudo-random bit sequence characterization using nonuniform periodic sampling in the presence of noiseThomas Moon, Nicholas Tzou, Xian Wang, Hyun Woo Choi, Abhijit Chatterjee. 146-151 [doi]
• Enhancing testability by structured partial scanPeter Wohl, John A. Waicukauski, J. E. Colburn. 152-157 [doi]
• Write-through method for embedded memory with compression Scan-based testingGeewhun Seok, Hong Kim, Baker Mohammad. 158-163 [doi]
• Ping-pong test: Compact test vector generation for reversible circuitsMasoud Zamani, Mehdi Baradaran Tahoori, Krishnendu Chakrabarty. 164-169 [doi]
• SAT-ATPG using preferences for improved detection of complex defect mechanismsAlexander Czutro, Matthias Sauer, Tobias Schubert, Ilia Polian, Bernd Becker. 170-175 [doi]
• Static test compaction for transition faults under the hazard-based detection conditionsIrith Pomeranz. 176-181 [doi]
• Exploiting X-correlation in output compression via superset X-cancelingJinsuk Chung, Nur A. Touba. 182-187 [doi]
• A novel method for fast identification of peak current during testWei Zhao, Sreejit Chakravarty, Junxia Ma, Narendra Devta-Prasanna, Fan Yang, Mohammad Tehranipoor. 191-196 [doi]
• A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuitsKohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara. 197-202 [doi]
• Power Characterization of Embedded SRAMs for Power BinningYang Zhao, Lisa Grenier, Amitava Majumdar. 203-208 [doi]
• Tester-based optical and electrical diagnostic system and techniquesPeilin Song, Franco Stellari. 209-214 [doi]
• A SMT-based diagnostic test generation method for combinational circuitsSarvesh Prabhu, Michael S. Hsiao, Loganathan Lingappan, Vijay Gangaram. 215-220 [doi]
• Net diagnosis using stuck-at and transition fault modelsLixing Zhao, Vishwani D. Agrawal. 221-226 [doi]
• Test algorithms for ECC-based memory repair in nanotechnologiesPanagiota Papavramidou, Michael Nicolaidis. 228-233 [doi]
• A Memory Failure Pattern Analyzer for memory diagnosis and repairBing-Yang Lin, Mincent Lee, Cheng-Wen Wu. 234-239 [doi]
• Process variability-aware proactive reconfiguration technique for mitigating aging effects in nano scale SRAM lifetimePeyman Pouyan, Esteve Amat, Antonio Rubio. 240-245 [doi]
• Are advanced DfT structures sufficient for preventing scan-attacks?Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre. 246-251 [doi]
• Proof carrying-based information flow tracking for data secrecy protection and hardware trustYier Jin, Yiorgos Makris. 252-257 [doi]
• Test generation for subtractive specification errorsPatricia S. Lee, Ian G. Harris. 258-263 [doi]
• On the parametric failures of SRAM in a 3D-die stack considering tier-to-tier supply cross-talkWen Yueh, Subho Chatterjee, Amit Ranjan Trivedi, Saibal Mukhopadhyay. 264-269 [doi]
• Transition delay fault testing of 3D ICs with IR-drop studyShreepad Panth, Sung Kyu Lim. 270-275 [doi]
• Estimating Power Supply Noise and its impact on path delaySushmita Kadiyala Rao, Chaitra Sathyanarayana, Ajay Kallianpur, Ryan Robucci, Chintan Patel. 276-281 [doi]
• Derating based hardware optimizations in soft error tolerant designsV. Prasanth, Virendra Singh, Rubin A. Parekhji. 282-287 [doi]
• Towards spatial fault resilience in array processorsSuraj Sindia, Vishwani D. Agrawal. 288-293 [doi]
• An aging-aware flip-flop design based on accurate, run-time failure predictionJunyoung Park, Jacob A. Abraham. 294-299 [doi]
• Advanced test methods for SRAMsAlberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel. 300-301 [doi]