Ying-Wen Chou, Po-Yuan Chen, Mincent Lee, Cheng-Wen Wu. Cost modeling and analysis for interposer-based three-dimensional IC. In 30th IEEE VLSI Test Symposium, VTS 2012, Maui, Hawaii, USA, 23-26 April 2012. pages 108-113, IEEE, 2012. [doi]
Abstract is missing.