Abstract is missing.
- Title Page [doi]
- Organizing Committee [doi]
- Additional Reviewers [doi]
- Program Committee [doi]
- Copyright [doi]
- Welcome Message [doi]
- Latency Lags BandwidthDavid A. Patterson. 3-6 [doi]
- Temperature-Dependent Optimization of Cache Leakage Power DissipationPeng Li, Yangdong Deng, Lawrence T. Pileggi. 7-12 [doi]
- Architectural Considerations for Energy EfficiencyHoang Q. Dao, Bart R. Zeydel, Vojin G. Oklobdzija. 13-16 [doi]
- Reducing the Latency and Area Cost of Core Swapping through Shared Helper EnginesAnahita Shayesteh, Eren Kursun, Timothy Sherwood, Suleyman Sair, Glenn Reinman. 17-23 [doi]
- Analytical Model for Sensor Placement on MicroprocessorsKyeong-Jae Lee, Kevin Skadron, Wei Huang. 24-30 [doi]
- Pre-layout Physical Connectivity Prediction with Application in Clustering-Based PlacementQinghua Liu, Malgorzata Marek-Sadowska. 31-37 [doi]
- Efficient Rectilinear Steiner Tree Construction with Rectilinear BlockagesZion Cien Shen, Chris C. N. Chu, Ying-Meng Li. 38-44 [doi]
- X-Routing using Two Manhattan Route InstancesSeraj Ahmad, Nikhil Jayakumar, Vijay Balasubramanian, Edward Hursey, Sunil P. Khatri, Rabi N. Mahapatra. 45-52 [doi]
- Hardware Support for Bulk Data Movement in Server PlatformsLi Zhao, Ravi R. Iyer, Srihari Makineni, Laxmi N. Bhuyan, Donald Newell. 53-60 [doi]
- Counter-Based Cache Replacement AlgorithmsMazen Kharbutli, Yan Solihin. 61-68 [doi]
- Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom DatapathsMehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski. 69-76 [doi]
- Are Today s Verification Tools Able to Handle Current Design Challenges?Rich Faris, Ken Larsen, Harry Foster, Stuart Swan. 77 [doi]
- Energy-Efficient Color Approximation for Digital LCD InterfacesAndi Nourrachmat, Sabino Salerno, Enrico Macii, Massimo Poncino. 81-86 [doi]
- Application-Specific Power-Aware Workload Allocation for Voltage Scalable MPSoC PlatformsMartino Ruggiero, Andrea Acquaviva, Davide Bertozzi, Luca Benini. 87-93 [doi]
- LCD Display Energy Reduction by User MonitoringVasily G. Moshnyaga, Eiji Morikawa. 94-97 [doi]
- Frame Buffer Energy Optimization by Pixel PredictionKimish Patel, Enrico Macii, Massimo Poncino. 98-101 [doi]
- Energy and Performance Analysis of Mapping Parallel Multithreaded Tasks for An On-Chip Multi-Processor SystemBo-Cheng Charles Lai, Patrick Schaumont, Wei Qin, Ingrid Verbauwhede. 102-104 [doi]
- Near-memory Caching for Improved Energy ConsumptionNevine AbouGhazaleh, Bruce R. Childers, Daniel Mossé, Rami G. Melhem. 105-110 [doi]
- Physical Synthesis of Energy-Efficient Networks-on-Chip Through Topology Exploration and Wire Style OptimizationzYuanfang Hu, Hongyu Chen, Yi Zhu, Andrew A. Chien, Chung-Kuan Cheng. 111-118 [doi]
- A Formal Framework for Modeling and Analysis of System-Level Dynamic Power ManagementShrirang M. Yardi, Karthik Channakeshava, Michael S. Hsiao, Thomas L. Martin, Dong S. Ha. 119-126 [doi]
- Efficient Implementation Selection via Time Budgeting Complexity Analysis and Leakage Optimization Case StudySoheil Ghiasi. 127-129 [doi]
- Efficient Thermal Simulation for Run-Time Temperature Tracking and ManagementHang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang. 130-136 [doi]
- A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCsAnuja Sehgal, Sule Ozev, Krishnendu Chakrabarty. 137-142 [doi]
- Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan TreeGang Zeng, Hideo Ito. 143-146 [doi]
- ChiYun Compact: A Novel Test Compaction Technique for Responses with Unknown ValuesMango Chia-Tso Chao, Seongmoon Wang, Srimat T. Chakradhar, Kwang-Ting Cheng. 147-152 [doi]
- Accurate Diagnosis of Multiple FaultsYung-Chieh Lin, Feng Lu, Kwang-Ting Cheng. 153-156 [doi]
- Quick Scan Chain Diagnosis Using Signal ProfilingJheng-Syun Yang, Shi-Yu Huang. 157-160 [doi]
- Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF CircuitsFang Liu, Sule Ozev. 161-170 [doi]
- Fault Tolerant Asynchronous Adder through Dynamic Self-reconfigurationSong Peng, Rajit Manohar. 171-179 [doi]
- Error-tolerance memory Microarchitecture via Dynamic MultithreadingLei Wang. 179-184 [doi]
- A Soft Error Monitor Using Switching Current DetectionPatrick Ndai, Amit Agarwal, Qikai Chen, Kaushik Roy. 185-192 [doi]
- Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP ImplementationErnst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler. 193-199 [doi]
- Statistical Analysis Driven Synthesis of Asynchronous SystemsKoji Ohashi, Mineo Kaneko. 200-205 [doi]
- Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath SynthesisNilanjan Banerjee, Arijit Raychowdhury, Swarup Bhunia, Hamid Mahmoodi-Meimand, Kaushik Roy. 206-214 [doi]
- Exploiting Vanishing Polynomials for Equivalence Veri.cation of Fixed-Size Arithmetic DatapathsNamrata Shekhar, Priyank Kalla, Sivaram Gopalakrishnan, Florian Enescu. 215-220 [doi]
- Incorporating Ef.cient Assertion Checkers into Hardware EmulationMarc Boule, Zeljko Zilic. 221-228 [doi]
- Assertion Checking of Behavioral Descriptions with Non-linear SolverIñigo Ugarte, Pablo Sanchez. 229-231 [doi]
- File System Interfaces for Embedded Software DevelopmentBhanu Pisupati, Geoffrey Brown. 232-238 [doi]
- Yesterday and Tomorrow: A View on Progress in Computer DesignMichael J. Flynn. 239-242 [doi]
- Ripple-Precharge TCAM A Low-Power Solution for Network Search EnginesDeepak S. Vijayasarathi, Mehrdad Nourani, Mohammad J. Akhbarizadeh, Poras T. Balsara. 243-248 [doi]
- Low- and Ultra Low-Power Arithmetic Units: Design and ComparisonMilena Vratonjic, Bart R. Zeydel, Vojin G. Oklobdzija. 249-252 [doi]
- A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in MicroprocessorsMuhammad M. Khellah, Maged Ghoneima, James Tschanz, Yibin Ye, Nasser Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail. 253-257 [doi]
- Low-Power Design of 90-nm SuperH Processor CoreTetsuya Yamada, Masahide Abe, Yusuke Nitta, Kenji Ogura, Manabu Kusaoke, Makoto Ishikawa, Motokazu Ozawa, Kiwamu Takada, Fumio Arakawa, Osamu Nishii, Toshihiro Hattori. 258-266 [doi]
- Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC FlowBradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton. 267-274 [doi]
- Algorithmic and Architectural Design Methodology for Particle Filters in HardwareAswin C. Sankaranarayanan, Rama Chellappa, Ankur Srivastava. 275-280 [doi]
- ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based NanotechnologyWei Zhang, Niraj K. Jha. 281-288 [doi]
- Automatic Synthesis of Composable Sequential Quantum Boolean CircuitsLi-Kai Chang, Fu-Chiung Cheng. 289-296 [doi]
- Model Checking C Programs Using F-SOFTFranjo Ivancic, Ilya Shlyakhter, Aarti Gupta, Malay K. Ganai. 297-308 [doi]
- Dealing with I/O Devices in the Context of Pervasive System VerificationMark A. Hillebrand, Thomas In der Rieden, Wolfgang J. Paul. 309-316 [doi]
- Towards the Formal Verification of Lower System Layers in Automotive SystemsSven Beyer, Peter Böhm, Michael Gerke 0002, Mark A. Hillebrand, Thomas In der Rieden, Steffen Knapp, Dirk Leinenbach, Wolfgang J. Paul. 317-326 [doi]
- Restrictive Compression Techniques to Increase Level 1 Cache CapacityPrateek Pujara, Aneesh Aggarwal. 327-333 [doi]
- The TM3270 Media-Processor Data CacheJan-Willem van de Waerdt, Stamatis Vassiliadis, Jean-Paul van Itegem, Hans Van Antwerpen. 334-341 [doi]
- Mitigating Soft Errors in Highly Associative Cache with CAM-based TagLuong Dinh Hung, Masahiro Goshima, Shuichi Sakai. 342-350 [doi]
- VGTA: Variation Aware Gate Timing AnalysisSoroush Abbaspour, Hanif Fatemi, Massoud Pedram. 351-356 [doi]
- Exact lower bound for the number of switches in series to implement a combinational logic cellFelipe Ribeiro Schneider, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis. 357-362 [doi]
- A Waveform Independent Gate Model for Accurate Timing AnalysisPeng Li, Emrah Acar. 363-365 [doi]
- Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate AnalysisFei Hu, Vishwani D. Agrawal. 366-372 [doi]
- Methods for Modeling Resource Contention on Simultaneous Multithreading ProcessorsTipp Moseley, Dirk Grunwald, Joshua L. Kihm, Daniel A. Connors. 373-380 [doi]
- Using Scratchpad to Exploit Object Locality in JavaCarl S. Lebsack, J. Morris Chang. 381-386 [doi]
- Correlation between Detailed and Simplified Simulations in Studying Multiprocessor ArchitectureKhaled Z. Ibrahim. 387-392 [doi]
- Simulating Commercial Java Throughput Workloads: A Case StudyYue Luo, Lizy Kurian John. 393-398 [doi]
- Minimum Energy Near-threshold Network of PLA based DesignNikhil Jayakumar, Sunil P. Khatri. 399-404 [doi]
- Robust Design of High Fan-In/Out Subthreshold CircuitsJinhui Chen, Lawrence T. Clark, Yu Cao. 405-410 [doi]
- A Thermally-Aware Methodology for Design-Specific Optimization of Supply and Threshold Voltages in Nanometer Scale ICsSheng-Chih Lin, Navin Srivastava, Kaustav Banerjee. 411-416 [doi]
- A Feasibility Study of Subthreshold SRAM Across Technology GenerationsArijit Raychowdhury, Saibal Mukhopadhyay, Kaushik Roy. 417-424 [doi]
- Variability-Driven Buffer Insertion Considering CorrelationsAzadeh Davoodi, Ankur Srivastava. 425-430 [doi]
- A Dual Dielectric Approach for Performance Aware Gate Tunneling Reduction in Combinational CircuitsValmiki Mukherjee, Saraju P. Mohanty, Elias Kougianos. 431-437 [doi]
- Supply Voltage Degradation Aware Analytical PlacementAndrew B. Kahng, Bao Liu, Qinke Wang. 437-443 [doi]
- Layout-Aware RF Circuit Synthesis Driven by Worst Case Parasitic CornersAnuradha Agarwal, Ranga Vemuri. 444-452 [doi]
- Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable FaultsManan Syal, Rajat Arora, Michael S. Hsiao. 453-460 [doi]
- Case Study of ATPG-based Bounded Model Checking: Verifying USB2.0 IP CoreQiang Qiang, Chia-Lun Chang, Daniel G. Saab, Jacob A. Abraham. 461-463 [doi]
- Towards finding path delay fault tests with high test efficiency using ZBDDsMaria K. Michael, Kyriakos Christou, Spyros Tragoudas. 464-467 [doi]
- Quality Transition Fault Tests Suitable for Small Delay DefectsMahilchi Milir Vaseekar Kumar, Spyros Tragoudas. 468-470 [doi]
- A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable SignalsNarendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz. 471-474 [doi]
- At-Speed Logic BIST Architecture for Multi-Clock DesignsLaung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo. 475-478 [doi]
- Hardware Ef.cient LBISTWith Complementary WeightsLiyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng. 479-484 [doi]
- FRAM Memory Technology - Advantages for Low Power, Fast Write, High Endurance ApplicationsRick Bailey, Glen Fox, Jarrod Eliason, Marty Depner, Daesig Kim, Edwin Jabillo, John Groat, John Walbert, Scott Summerfelt, K. R. Udayakumar, John Rodriquez, Keith Remack, K. Boku, John Gertas. 485 [doi]
- A High Performance Sub-Pipelined Architecture for AESHua Li, Jianzhou Li. 491-496 [doi]
- Surfliner: A Distortionless Electrical Signaling Scheme for Speed of Light On-Chip CommunicationsHongyu Chen, Rui Shi, Chung-Kuan Cheng, David M. Harris. 497-502 [doi]
- Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing AlgorithmKazunori Shimizu, Tatsuyuki Ishikawa, Takeshi Ikenaga, Satoshi Goto, Nozomu Togawa. 503-510 [doi]
- Fast Minimum and Maximum SelectionAnatoly I. Grushin. 511-518 [doi]
- Three-Dimensional Cache Design Exploration Using 3DCactiYuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. 519-524 [doi]
- Implementing Caches in a 3D Technology for High Performance ProcessorsKiran Puttaswamy, Gabriel H. Loh. 525-532 [doi]
- Architectural-Level Fault Tolerant Computation in Nanoelectronic ProcessorsWenjing Rao, Alex Orailoglu, Ramesh Karri. 533-542 [doi]
- Formal Verification and its Impact on the Snooping versus Directory Protocol DebateMilo M. K. Martin. 543-449 [doi]
- Deployment of Better Than Worst-Case Design: Solutions and NeedsTodd M. Austin, Valeria Bertacco. 550-558 [doi]
- Benefits and Costs of Power-Gating TechniqueHailin Jiang, Malgorzata Marek-Sadowska, Sani R. Nassif. 559-566 [doi]
- A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOSMaryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De. 567-573 [doi]
- A Low-Overhead Virtual Rail Technique for SRAM Leakage Power ReductionJente B. Kuang, Hung C. Ngo, Kevin J. Nowka, J. C. Law, Rajiv V. Joshi. 574-584 [doi]
- State Set Management for SAT-based Unbounded Model CheckingKameshwar Chandrasekar, Michael S. Hsiao. 585-590 [doi]
- Reconsidering CEGAR: Learning Good Abstractions without RefinementAnubhav Gupta, Edmund M. Clarke. 591-598 [doi]
- Formal Verification of Parametric Multiplicative Division ImplementationsNikhil Kikkeri, Peter-Michael Seidel. 599-602 [doi]
- Challenges in the Formal Verification of Complete State-of-the-Art ProcessorsNathaniel Ayewah, Nikhil Kikkeri, Peter-Michael Seidel. 603-608 [doi]
- RECAST: Boosting Tag Line Buffer Coverage in Low-Power High-Level Caches for Free Won-Ho Park, Andreas Moshovos, Babak Falsafi. 609-616 [doi]
- Load-Store Queue Management: an Energy-Efficient Design Based on a State-Filtering Mechanism.Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang. 617-624 [doi]
- Optimizing the Thermal Behavior of Subarrayed Data CachesJohnsy K. John, Jie S. Hu, Sotirios G. Ziavras. 625-630 [doi]
- VALVE: Variable Length Value Encoder for Off-Chip Data Buses.Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang. 631-633 [doi]
- Monitoring Temperature in FPGA based SoCsSivakumar Velusamy, Wei Huang, John Lach, Mircea R. Stan, Kevin Skadron. 634-640 [doi]
- Reducing the Energy of Speculative Instruction SchedulersYongxiang Liu, Gokhan Memik, Glenn Reinman. 641-646 [doi]
- A New Pointer-based Instruction Queue Design and Its Power-Performance EvaluationMarco A. Ramírez, Adrián Cristal, Mateo Valero, Alexander V. Veidenbaum, Luis Villa. 647-653 [doi]
- Power-Efficient Wakeup Tag BroadcastJoseph J. Sharkey, Kanad Ghose, Dmitry V. Ponomarev, Oguz Ergin. 654-661 [doi]
- SST: Symbolic Subordinate ThreadingRania Mameesh, Manoh Franklin. 662-665 [doi]
- Memory Bank PredictorsStefan Bieschewski, Joan-Manuel Parcerisa, Antonio González. 666-670 [doi]
- H-SIMD Machine: Configurable Parallel Computing for Matrix MultiplicationXizhen Xu, Sotirios G. Ziavras. 671-676 [doi]
- Temperature-Sensitive Loop Parallelization for Chip MultiprocessorsSri Hari Krishna Narayanan, Guilin Chen, Mahmut T. Kandemir, Yuan Xie. 677-682 [doi]
- Broadband Impedance Matching for Inductive Interconnect in VLSI PackagesBrock J. LaMeres, Sunil P. Khatri. 683-688 [doi]
- Temperature-Aware Voltage Islands Architecting in System-on-Chip DesignWei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner. 689-696 [doi]
- Temporal Decomposition for Logic OptimizationNathan Kitchen, Andreas Kuehlmann. 697-702 [doi]
- Attacking Control Overhead to Improve Synthesised Asynchronous Circuit PerformanceLuis A. Plana, Sam Taylor, Doug Edwards. 703-710 [doi]
- An Improved Approach for AlternativeWires Identi.cationYung-Chih Chen, Chun-Yao Wang. 711-716 [doi]