Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo. At-Speed Logic BIST Architecture for Multi-Clock Designs. In 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA. pages 475-478, IEEE Computer Society, 2005. [doi]
Abstract is missing.