A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer - researchr publication

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Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy. A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. In Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005. pages 9, IEEE, 2005. [doi]

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