Table of Contents

• ATPG-based cost-effective, secure logic lockingAbhrajit Sengupta, Mohammed Thari Nabeel, Muhammad Yasin, Ozgur Sinanoglu. 1-6 [doi]
• A built-in self-test technique for transmitter-only systemsMaryam Shafiee, Jennifer N. Kitchen, Sule Ozev. 1-6 [doi]
• RF circuit authentication for detection of process TrojansFatih Karabacak, Richard Welker, Matthew J. Casto, Jennifer N. Kitchen, Sule Ozev. 1-6 [doi]
• Special session on intelligent sensor nodesKanad Basu, Shreyas Sen, Kanad Basu, Shreyas Sen. 1 [doi]
• Innovative practices on machine learning for emerging applicationsKareem Madkour, Zhaobo Zhang, Alfred L. Crouch, Peter L. Levin, Eve Hunter, Yu Huang. 1 [doi]
• An oscillation-based test technique for on-chip testing of mm-wave phase shiftersMarc Margalef-Rovira, Manuel J. Barragan, Ekta Sharma, Philippe Ferrari, Emmanuel Pistono, Sylvain Bourdel. 1-6 [doi]
• Efficient parallel testing: A configurable and scalable broadcast network design using IJTAGSaurabh Gupta, Jae Wu, Jennifer Dworak. 1-6 [doi]
• Special session: How approximate computing impacts verification, test and reliabilityLukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, D. Oliveria, F. Fernandes, S. Di Carlo. 1 [doi]
• Innovative practices on functional testing and fault simulation for FuSaAnandh Krishnan, John van Gelder, Mayukh Bhattacharya, Sreejit Chakravarty, Prashant Goteti. 1 [doi]
• Hardware Trojan attacks in embedded memoryTamzidul Hoque, Xinmu Wang, Abhishek Basak, Robert Karam, Swarup Bhunia. 1-6 [doi]
• An inter-layer interconnect BIST solution for monolithic 3D ICsAbhishek Koneru, Krishnendu Chakrabarty. 1-6 [doi]
• IP session on ISO26262 EDAArt Schaldenbrand, Yervant Zorian, Stephen Sunter, Peter Sarson. 1 [doi]
• Staggered ATPG with capture-per-cycle observation test pointsYingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer. 1-6 [doi]
• On-line monitoring and error correction in sensor interface circuits using digital calibration techniquesSascha Heinssen, Theodor Hillebrand, Maike Taddiken, Steffen Paul, Dagmar Peters-Drolshagen. 1-6 [doi]
• Real-time monitoring of test fallout data to quickly identify tester and yield issues in a multi-site environmentQutaiba Khasawneh, Jennifer Dworak, Ping Gui, Benjamin Williams, Alan C. Elliott, Anand Muthaiah. 1-6 [doi]
• Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUFJing Ye, Qingli Guo, Yu Hu, Huawei Li, Xiaowei Li. 1-6 [doi]
• Special session on quantum systems: Next challenges in design, test, integrationCarlo Reita, Jonathan Baugh, Gabriel Poulin-Lamarre, Bozena Kaminska, Bernard Courtois. 1 [doi]
• Securing IJTAG against data-integrity attacksRana Elnaggar, Ramesh Karri, Krishnendu Chakrabarty. 1-6 [doi]
• Fast fault coverage estimation of sequential tests using entropy measurementsMichael S. Hsiao, Sarmad Tanwir. 1-6 [doi]
• Innovative practices on challenges, opportunities, and solutions to hardware securitySohrab Aftabjahani, Jason Oberg, Michael Chen, Huawei Li. 1 [doi]
• NOIDA: Noise-resistant Intra-cell DiagnosisSoumya Mittal, R. D. (Shawn) Blanton. 1-6 [doi]
• Test challenges and solutions for emerging non-volatile memoriesMohammad Nasim Imtiaz Khan, Swaroop Ghosh. 1-6 [doi]
• Innovative practices on test in JapanKoji Asami, Yoshiro Tamura, Haruo Kobayashi, Jun Matsushima, Yoichi Maeda, Kazumi Hatayama. 1 [doi]
• Broadcast-based minimization of the overall access time for the IEEE 1687 networkZhanwei Zhong, Guoliang Li, Qinfu Yang, Jun Qian, Krishnendu Chakrabarty. 1-6 [doi]
• Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuitsOmar Al-Terkawi Hasib, Daniel Crepeau, Thomas Awad, Andrei Dulipovici, Yvon Savaria, Claude Thibeault. 1-6 [doi]
• Systematic b-adjacent symbol error correcting reed-solomon codes with parallel decodingAbhishek Das, Nur A. Touba. 1-6 [doi]
• A coherent subsampling test system arrangement suitable for phase domain measurementsYoung Gouk Cho, Gordon W. Roberts, Sadok Aouini, Mahdi Parvizi, Naim Ben Hamida. 1-6 [doi]
• Special session on bringing cores closer together: The wireless revolution in on-chip communicationTerrence Mak, Hiroki Matsutani, Partha Pratim Pande. 1 [doi]
• Innovative practices on silicon photonicsRoy Meade, Woosung Kim, Richard Otte, Eugene Atwood. 1 [doi]
• IR drop prediction of ECO-revised circuits using machine learningShih-Yao Lin, Yen-Chun Fang, Yu-Ching Li, Yu-cheng Liu, Tsung-Shan Yang, Shang-Chien Lin, Chien-Mo James Li, Eric Jia-Wei Fang. 1-6 [doi]
• Innovative practices on quality levels of A/MS devicesWim Dobbelaere, On Semi, Massimo Violante, Turin Polytechnic, Jeff Rearick. 1 [doi]
• Online information utility assessment for per-device adaptive test flowYanjun Li, Ender Yilmaz, Peter Sarson, Sule Ozev. 1-6 [doi]
• Group delay measurement of frequency down-converter devices using chirped RF modulated signalPeter Sarson, Tomonori Yanagida, Kosuke Machida. 1-6 [doi]
• Special session on machine learning: How will machine learning transform test?Yiorgos Makris, Amit Nahar, Haralampos-G. D. Stratigopoulos, Marc Hutner. 1 [doi]
• Special session: Recent developments in hardware securityRo Commarota, Naghmeh Karimi, Siddharth Garg, Jeyavijayan Rajendran. 1 [doi]
• Special session on overcoming reliability and energy-efficiency challenges with silicon photonics for future manycore computingSudeep Pasricha, Davide Bertozzi, Hui Li. 1 [doi]
• Special session on reliability and vulnerability of neuromorphic computing systemsShimeng Yu, Chenchen Liu, Wujie Wen, Yiran Chen. 1 [doi]
• Circuit-level reliability simulator for front-end-of-line and middle-of-line time-dependent dielectric breakdown in FinFET technologyKexin Yang, Taizhi Liu, Rui Zhang, Linda Milor. 1-6 [doi]
• Innovative practices on design & test for flexible hybrid electronicsTsung-Ching Jim Huang, Jason Marsh, Scott H. Goodwin, Dorota S. Temple, Tsung-Ching Jim Huang. 1 [doi]
• Efficient generation of parametric test conditions for AMS chips with an interval constraint solverFelix Neubauer, Jan Burchard, Pascal Raiola, Jochen Rivoir, Bernd Becker 0001, Matthias Sauer 0002. 1-6 [doi]
• Modeling and test generation for combinational hardware TrojansZiqi Zhou, Ujjwal Guin, Vishwani D. Agrawal. 1-6 [doi]
• IC layout weak point effectiveness evaluation based on statistical methodsFang Lin, Ali Ahmadi, Kannan Sekar, Yan Pan, Ke Huang. 1-6 [doi]
• Special session on BIST/calibration of A/MS devicesHans-Mart von Staudt, James Izon, Sule Ozev, Peter Sarson. 1 [doi]
• Multi-faceted microarchitecture level reliability characterization for NVIDIA and AMD GPUsAlessandro Vallero, Sotiris Tselonis, Dimitris Gizopoulos, Stefano Di Carlo. 1-6 [doi]
• Innovative practices on memory test practiceM. Casarsa, Gurgen Harutyunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarthy, Ramesh Tekumalla. 1 [doi]
• Enhanced hotspot detection through synthetic pattern generation and design of experimentsGaurav Rajavendra Reddy, Constantinos Xanthopoulos, Yiorgos Makris. 1-6 [doi]
• Special session on machine learning for test and diagnosisKrishnendu Chakrabarty, Li-C. Wang, Gaurav Veda, Yu Huang. 1 [doi]
• High efficient low cost EEPROM screening method in combination with an area optimized byte replacement strategy which enables high reliability EEPROMsGregor Schatzberger, Friedrich Peter Leisenberger, Peter Sarson, Andreas Wiesner. 1-6 [doi]
• Analyzing and mitigating the impact of permanent faults on a systolic array based neural network acceleratorJeff Jun Zhang, Tianyu Gu, Kanad Basu, Siddharth Garg. 1-6 [doi]