Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST

Fahad Ahmed, Linda Milor. Reliable cache design with on-chip monitoring of NBTI degradation in SRAM cells using BIST. In 28th IEEE VLSI Test Symposium, VTS 2010, April 19-22, 2010, Santa Cruz, California, USA. pages 63-68, IEEE Computer Society, 2010. [doi]

Abstract

Abstract is missing.