Table of Contents

• Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAsSean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong. 1-9 [doi]
• A Machine Learning Approach for Power Gating the FPGA Routing NetworkZeinab Seifoori, Hossein Asadi, Mirjana Stojilovic. 10-18 [doi]
• Exploring Resource-Efficient Acceleration Algorithm for Transposed Convolution of GANs on FPGAXinkai Di, Haigang Yang, Zhihong Huang, Ning Mao, Yiping Jia, Yong Zheng. 19-27 [doi]
• Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGAHongxiang Fan, Gang Wang, Martin Ferianc, Xinyu Niu, Wayne Luk. 28-35 [doi]
• SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level SynthesisJulian Oppermann, Lukas Sommer, Lukas Weber, Melanie Reuter-Oppermann, Andreas Koch 0001, Oliver Sinnen. 36-44 [doi]
• Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAsYiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu 0001. 45-53 [doi]
• Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated ProgramsMatthew B. Ashcraft, Jeffrey Goeders. 54-62 [doi]
• An Open Source FPGA-Optimized Out-of-Order RISC-V Soft ProcessorSusumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima. 63-71 [doi]
• Time-SWAD: A Dataflow Engine for Time-Based Single Window Stream AggregationPrajith Ramakrishnan Geethakumari, Vincenzo Gulisano, Pedro Trancoso, Ioannis Sourdis. 72-80 [doi]
• A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable MemoryTakeharu Ikezoe, Takuya Kojima, Hideharu Amano. 81-89 [doi]
• Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product QuantizationAmeer M. S. Abdelhadi, Christos-Savvas Bouganis, George A. Constantinides. 90-98 [doi]
• OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAsPaolo Gorlani, Tobias Kenter, Christian Plessl. 99-107 [doi]
• Pipelined Parallel Finite Automata EvaluationVipula Sateesh, Connor Mckeon, Jared Winograd, André DeHon. 108-116 [doi]
• ZFP-V: Hardware-Optimized Lossy Floating Point CompressionGongjin Sun, Sang-Woo Jun. 117-125 [doi]
• Merge-Exchange Sort Based Discrete Gaussian Sampler with Fixed Memory Access PatternShanquan Tian, Wen Wang 0007, Jakub Szefer. 126-134 [doi]
• An Overlay for Rapid FPGA Debug of Machine Learning ApplicationsDaniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton. 135-143 [doi]
• Partitioning FPGA-Optimized Systolic Arrays for Fun and ProfitLong Chung Chan, Gurshaant Malik, Nachiket Kapre. 144-152 [doi]
• Reducing FPGA Compile Time with Separate Compilation for FPGA Building BlocksYuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon. 153-161 [doi]
• Enhanced Heterogeneous Cloud: Transparent Acceleration and ElasticityJessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik. 162-170 [doi]
• An Open-Source Lightweight Timing Model for RapidWrightPongstorn Maidee, Chris Neely, Alireza Kaviani, Chris Lavin. 171-178 [doi]
• Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ SystemsKristiyan Manev, Anuj Vaishnav, Dirk Koch. 179-187 [doi]
• In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGAGabor Csordas, Mikhail Asiatici, Paolo Ienne. 188-196 [doi]
• Shrink It or Shed It! Minimize the Use of LSQs in Dataflow DesignsLana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne. 197-205 [doi]
• Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware CodesignViet B. Dang, Farnoud Farahmand, Michal Andrzejczak, Kris Gaj. 206-214 [doi]
• A High Performance FPGA-Based Accelerator Design for End-to-End Speaker Recognition SystemMingjun Jiao, Yue Li, Pengbo Dang, Wei Cao, Lingli Wang. 215-223 [doi]
• High-Throughput and Low-Latency Distributed Management Proxy for Key-Value Store Over 100Gbps Ethernet on FPGAJinyu Xie, Yunhui Qiu, Wenbo Yin, Lingli Wang. 224-230 [doi]
• Optimized Polynomial Multiplier Over Commutative Rings on FPGAs: A Case Study on BIKEJingwei Hu, Wen Wang, Ray C. C. Cheung, Huaxiong Wang. 231-234 [doi]
• An OpenCL-Based FPGA Accelerator for Compressed YOLOv2Anrong Yang, Yuanhui Li, Hongqiao Shu, Jianlin Deng, Chuanzhao Ma, Zheng Li, Qigang Wang. 235-238 [doi]
• Secure Internal Communication of a Trustzone-Enabled Heterogeneous Soc Lightweight EncryptionEl Mehdi Benhani, Cuauhtemoc Mancillas-López, Lilian Bossuet. 239-242 [doi]
• Amoeba-Inspired Hardware SAT Solver with Effective Feedback ControlAnh Hoang Ngoc Nguyen, Masashi Aono, Yuko Hara-Azumi. 243-246 [doi]
• A Study on Switch Block Patterns for Tileable FPGA Routing ArchitecturesXifan Tang, Edouard Giacomin, Aurélien Alacchi, Pierre-Emmanuel Gaillardon. 247-250 [doi]
• Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAsLukas Weber, Lukas Sommer, Julian Oppermann, Alejandro Molina 0001, Kristian Kersting, Andreas Koch 0001. 251-254 [doi]
• SpWMM: A High-Performance Sparse-Winograd Matrix-Matrix Multiplication Accelerator for CNNsDi Wu, Wei Cao, Lingli Wang. 255-258 [doi]
• Network Enabled Partial Reconfiguration for Distributed FPGA Edge AccelerationAlex R. Bucknall, Shanker Shreejith, Suhaib A. Fahmy. 259-262 [doi]
• A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text RecognitionShirui Zhao, Fengwei An, Hao Yu 0001. 263-266 [doi]
• A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGAYouki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara. 267-270 [doi]
• A High Energy-Efficiency FPGA-Based LSTM Accelerator Architecture Design by Structured Pruning and Normalized Linear QuantizationYong Zheng, Haigang Yang, Zhihong Huang, Tianli Li, Yiping Jia. 271-274 [doi]
• ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in High-Level SynthesisNicholas V. Giamblanco, Jason Helge Anderson. 275-278 [doi]
• Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming ModelsDaniele Passaretti, Jan Moritz Joseph, Thilo Pionteck. 279-282 [doi]
• An OpenCL-Based Hybrid CNN-RNN Inference Accelerator On FPGAYunfei Sun, Brian Liu, Xianchao Xu. 283-286 [doi]
• A Resource Consumption and Performance Overhead Optimized Reduction Circuit on FPGAsLinhuai Tang, Gang Cai, Tao Yin, Yong Zheng, Jiamin Chen. 287-290 [doi]
• Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element UsageBo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen. 291-294 [doi]
• A Complete CPU-FPGA Architecture for Protein Identification with Tandem Mass SpectrometryMoucheng Yang, Tao Chen 0005, Xuegong Zhou, Liang Zhao, Yunping Zhu, Lingli Wang. 295-298 [doi]
• Real-Time Automatic Modulation ClassificationStephen Tridgell, David Boland, Philip H. W. Leong, Siddhartha 0003. 299-302 [doi]
• Automatic Generation of Application-Specific FPGA Overlays with RapidWrightJoel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, Christophe Bobda. 303-306 [doi]
• Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAsEriko Nurvitadhi, Mishali Naik, Andrew Boutros, Prerna Budhkar, Ali Jafari, Dongup Kwon, David Sheffield, Abirami Prabhakaran, Karthik Gururaj, Pranavi Appana. 307-310 [doi]
• RNA: Reconfigurable LSTM Accelerator with Near Data Approximate ProcessingYu Gong, Bo Liu 0026, Wei Ge, Longxing Shi. 311-314 [doi]
• OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAsCheng Liu, Xinyu Chen, Bingsheng He, Xiaofei Liao, Ying Wang, Lei Zhang. 315-318 [doi]
• AutoBoxing: Improving GCC Passes to Optimize HW/SW Multi-Versioning of Kernels for HLSJohanna Rohde, Christian Hochberger. 319-322 [doi]
• ZyNet: Automating Deep Neural Network Implementation on Low-Cost Reconfigurable Edge Computing PlatformsKizheppatt Vipin. 323-326 [doi]
• Power-Aware FPGA Mapping of Convolutional Neural NetworksAlexander Montgomerie-Corcoran, Stylianos I. Venieris, Christos-Savvas Bouganis. 327-330 [doi]
• HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-WiresYukui Luo, Xiaolin Xu. 331-334 [doi]
• Storage Mirroring for Bare-Metal Malware Analysis on FPGA DevicesDan Cristian Turicu, Octavian Cret, Lucia Vacariu. 335-338 [doi]
• MajorityNets: BNNs Utilising Approximate Popcount for Improved EfficiencySeyedRamin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong. 339-342 [doi]
• Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSEAndré Bannwart Perina, Jürgen Becker 0001, Vanderlei Bonato. 343-346 [doi]
• Evaluation of Partially Constant, Fine-Grained, Dynamic Partial Reconfigurable Functions in FPGAsStefan Brennsteiner, Tughrul Arslan, John S. Thompson. 347-350 [doi]
• Optimizing FPGA-Based Streaming Applications for Throughput Using PipeliningAli Asghar, Rick van Loo, Timon Kruiper, Daniel Ziener. 351-354 [doi]
• Lightweight Programmable DSP Block Overlay for Streaming Neural Network AccelerationLenos Ioannou, Suhaib A. Fahmy. 355-358 [doi]
• Optimisation of System Throughput Exploiting Tasks Heterogeneity on Space Shared FPGAsUmar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis. 359-362 [doi]
• Hybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA ClusterTomohiro Ueno, Takaaki Miyajima, Antoniette Mondigo, Kentaro Sano. 363-366 [doi]
• Efficient OS Hardware Accelerators Preemption Management in FPGAYe Tian, Jean-Christophe Prévotet, Fabienne Nouvel. 367-370 [doi]
• A High-Level Synthesis Approach to the Software/Hardware Codesign of NTT-Based Post-Quantum Cryptography AlgorithmsDuc Tri Nguyen, Viet B. Dang, Kris Gaj. 371-374 [doi]
• High-Level Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered RoutingYu-Ting Chen, Jin-Hee Kim, Kexin Li, Graham Hoyes, Jason H. Anderson. 375-378 [doi]
• Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTMZhiqiang Que, Yanyang Liu, Ce Guo, Xinyu Niu, Yongxin Zhu 0001, Wayne Luk. 379-382 [doi]
• Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online ArithmeticAmeer M. S. Abdelhadi, Lesley Shannon. 383-386 [doi]
• Implementation of Distributed Processing Using a PC-FPGA Hybrid SystemKeisuke Takano, Tetsuya Oda, Ryo Ozaki, Akira Uejima, Masaki Kohata. 387-390 [doi]
• SoC-FPGA-Based Implementation of Iris Recognition Enhanced by QC-LDPC CodesLongyu Ma, Chiu-Wing Sham. 391-394 [doi]
• Evolved Binary Neural Networks Through Harnessing FPGA CapabilitiesRaúl Valencia, Chiu-Wing Sham, Oliver Sinnen. 395-398 [doi]
• FPNet: Customized Convolutional Neural Network for FPGA PlatformsYang Yang, Chao Wang 0003, Lei Gong, Xuehai Zhou. 399-402 [doi]
• An Iterative Technique for Runtime Efficient Hardware-Software PartitioningDeshya Wijesundera, Kisaru Liyanage, Alok Prakash, Thambipillai Srikanthan, Thilina Perera. 403-406 [doi]
• Parallelization of Recursive Function in Ruby-Based High-Level SynthesisRyota Yamashita, Daichi Teruya, Hironori Nakajo. 407-410 [doi]
• Dependency-Aware Clustering for Variable-Grained Hardware-Software PartitioningDeshya Wijesundera, Nadeeshan Dissanayake, Alok Prakash, Thambipillai Srikanthan, Damith Anhettigama. 411-414 [doi]
• Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable ComputingLahiru Rasnayake, Magnus Själander. 415-418 [doi]
• Real-Time Object Detection on 640x480 Image With VGG16+SSDHyeong-Ju Kang. 419-422 [doi]
• Winograd-Based Real-Time Super-Resolution System on FPGABizhao Shi, Zhucheng Tang, Guojie Luo, Ming Jiang 0001. 423-426 [doi]
• An End-to-End Solution to Autonomous Driving Based on Xilinx FPGATianze Wu, Weiyi Liu, Yongwei Jin. 427-430 [doi]
• Autonomous Driving Developed with an FPGA DesignEuan Jones, Keegan Pepper, Aimei Li, Shiyue Li, Yuteng Zhang, Donald Bailey. 431-434 [doi]
• Self-Driving Car Application of a Stream-Oriented Accelerator FrameworkShimon Kudaka, Ai Suzuki, Natsumi Yamada, Noriki Oshiro, Taichi Miyagi, Yasunori Osana. 435-436 [doi]
• Towards the Improvement of Training Efficiency and Image Recognition Accuracy for an FPGA Controlled Mini-Car by Offloading Neural Network TrainingMusashi Aoto, Moe Mitsugi, Takumi Momose, Yasutaka Wada. 437-440 [doi]
• Design and Implementation of Autonomous Driving Robot Car Using SoC FPGAAkira Kojima, Yuya Osawa. 441-444 [doi]
• ZytleBot: FPGA Integrated Development Platform for ROS Based Autonomous Mobile RobotYasuhiro Nitta, Sou Tamura, Hidetoshi Yugen, Hideki Takase. 445-448 [doi]
• Autonomous Vehicle Development Using FPGA for Image ProcessingHamish Simmonds, Nicholas Carlisle, Xue Li, Fanglin Mu, Donald Bailey. 449-452 [doi]
• Development of Autonomous Driving System Using Programmable SoCsTomonari Tanaka, Itsuki Ikeno, Riku Tsuruoka, Takumi Kuchiba, Wang Liao, Yukio Mitsuyama. 453-456 [doi]
• Implementation of a ROS-Based Autonomous Vehicle on an FPGA BoardKento Hasegawa, Kazunari Takasaki, Makoto Nishizawa, Ryota Ishikawa, Kazushi Kawamura, Nozomu Togawa. 457-460 [doi]
• Autonomous Vehicle Driving Using the Stream-Based Real-Time Hardware Line DetectorTaito Manabe, Naofumi Yoshinaga, Yuta Imamura, Taichi Saikai, Koki Fujita, Masatomo Matsuda, Kotoko Miyata, Tatsuma Mori, Yuichiro Shibata, Hiroki Egawa, Yuichi Kawamata, Tomohiro Kida, Ryouhei Tsugami, Ryohei Kakizaki, Taichi Katayama, Koki Tomonaga, Shota Fukui. 461-464 [doi]
• FPGA-Based Object Detection for Autonomous Driving SystemKenichi Harada, Kenji Kanazawa, Moritoshi Yasunaga. 465-468 [doi]
• An SoC-FPGA-Based Micro UGV with Localization and Motion PlanningYuya Kudo, Atsushi Takada, Yuta Ishida, Tomonori Izumi. 469-472 [doi]
• Design and Development of Networked Multiple FPGA Components for Autonomous Tiny Robot CarTakeshi Ohkawa, Shotaro Tayama, Hayato Mori, Dohyung Lee, Hayato Amano, Itsuki Hirakawa, Mikiko Sato, Harumi Watanabe. 473-475 [doi]
• Image Processing and Vehicles - Using FPGA to Reduce Latency of Time Critical TasksAndrew Yeo, Damon Hill, Anzhen Huang, Xueao Liu, Guanchen Dong, Donald Bailey. 476-479 [doi]