Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL - researchr publication

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John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. In Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003. pages 688-690, ACM, 2003. [doi]

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