John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas. Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. In Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003. pages 688-690, ACM, 2003. [doi]
@inproceedings{ManeatisKMMS03,
title = {Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL},
author = {John G. Maneatis and Jaeha Kim and Iain McClatchie and Jay Maxey and Manjusha Shankaradas},
year = {2003},
doi = {10.1145/775832.776006},
url = {http://doi.acm.org/10.1145/775832.776006},
researchr = {https://researchr.org/publication/ManeatisKMMS03},
cites = {0},
citedby = {0},
pages = {688-690},
booktitle = {Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003},
publisher = {ACM},
isbn = {1-58113-688-9},
}