Abstract is missing.
- Architecture and Compiler Tradeoffs for a Long Instruction Word MicroprocessorRobert Cohn, Thomas R. Gross, Monica S. Lam, P. S. Tseng. 2-14
- Tradeoffs in Instruction Format Design for Horizontal ArchitecturesGurindar S. Sohi, Sriram Vajapeyam. 15-25
- Overlapped Loop Support in the Cydra 5James C. Dehnert, Peter Y.-T. Hsu, Joseph P. Bratt. 26-38
- Architectural Support for Synchronous Task CommunicationForbes J. Burkowski, Gordon V. Cormack, G. D. P. Dueck. 40-53
- The Fuzzy Barrier: A Mechanism for High Speed Synchronization of ProcessorsRajiv Gupta. 54-63
- Efficent Synchronization Primitives for Large-Scale Cache-Coherent MultiprocessorsJames R. Goodman, Mary K. Vernon, Philip J. Woest. 64-75
- Efficient Debugging Primitives for MultiprocessorsZiya Aral, Ilya Gertner, Greg Schaffer. 87-95
- Reference History, Page Size, and Migration Daemons in Local/Remote ArchitecturesMark A. Holliday. 104-112
- Failure Correction Techniques for Large Disk ArraysGarth A. Gibson, Lisa Hellerstein, Richard M. Karp, Randy H. Katz, David A. Patterson. 123-132
- A Unified Vector/Scalar Floating-Point ArchitectureNorman P. Jouppi, Jonathan Bertoni, David W. Wall. 134-143
- An Analysis of 8086 Instruction Set Usage in MS DOS ProgramsThomas L. Adams, Richard E. Zimmerman. 152-160
- The Run-Time Environment for Screme, A Scheme Implementation on the 88000Steven R. Vegdahl, Uwe F. Pleban. 172-182
- Program Optimization for Instruction CachesScott McFarling. 183-191
- Using Registers to Optimize Cross-Domain Call PerformancePaul A. Karger. 194-204
- The Design of Nectar: A Network Backplane for Heterogeneous MulticomputersEmmanuel A. Arnould, Francois J. Bitz, Eric C. Cooper, H. T. Kung, Robert D. Sansom, Peter Steenkiste. 205-216
- A Message Driven Or-Parallel MachineSergio A. Delgado-Rannauro, T. J. Reynolds. 217-228
- Evaluating the Performance of Software Cache CoherenceSusan S. Owicki, Anant Agarwal. 230-242
- Analysis of Cache Invalidation Patterns in MultiprocessorsWolf-Dietrich Weber, Anoop Gupta. 243-256
- The Effect of Sharing on the Cache and Bus Performance of Parallel ProgramsSusan J. Eggers, Randy H. Katz. 257-270
- Available Instruction-Level Parallelism for Superscalar and Superpipelined MachinesNorman P. Jouppi, David W. Wall. 272-282
- Micro-Optimization of Floating Point OperationsWilliam J. Dally. 283-289
- Limits on Multiple Instruction IssueMichael D. Smith, Mike Johnson, Mark Horowitz. 290-302