Table of Contents

• A memristor-based TCAM (Ternary Content Addressable Memory) cellPilin Junsangsri, Fabrizio Lombardi, Jie Han. 1-6 [doi]
• On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuronDjaafar Chabi, Zhaohao Wang, Weisheng Zhao, Jacques-Olivier Klein. 7-12 [doi]
• Sneak paths effects in CBRAM memristive devices arrays for spiking neural networksDavid Roclin, Olivier Bichler, Christian Gamrat, Jacques-Olivier Klein. 13-18 [doi]
• On the influence of synaptic weight states in a locally competitive algorithm for memristive hardwareWalt Woods, Jens Burger, Christof Teuscher. 19-24 [doi]
• System-level assessment and area evaluation of Spin Wave logic circuitsOdysseas Zografos, Praveen Raghavan, Luca Gaetano Amarù, Bart Soree, Rudy Lauwereins, Iuliana Radu, Diederik Verkest, Aaron Thean. 25-30 [doi]
• STT-MRAM based low power synchronous non-volatile logic with timing demultiplexingKejie Huang, Rong Zhao, Yong Lian. 31-36 [doi]
• Spin torque nano oscillators as key building blocks for the Systems-on-Chip of the futureMircea R. Stan, Mehdi Kabir, Stuart A. Wolf, Jiwei Lu. 37-38 [doi]
• Integration of threshold logic gates with RRAM devices for energy efficient and robust operationJinghua Yang, Niranjan Kulkarni, Shimeng Yu, Sarma B. K. Vrudhula. 39-44 [doi]
• HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory designPilin Junsangsri, Fabrizio Lombardi, Jie Han. 45-50 [doi]
• Compression architecture for bit-write reduction in non-volatile memory technologiesDavid B. Dgien, Poovaiah M. Palangappa, Nathan A. Hunter, Jiayin Li, Kartik Mohanram. 51-56 [doi]
• A new Tunnel-FET based RAM concept for ultra-low power applicationsMostafizur Rahman, Mingyu Li, Jiajun Shi, Santosh Khasanvis, Csaba Andras Moritz. 57-58 [doi]
• Analog-to-stochastic converter using magnetic-tunnel junction devicesNaoya Onizawa, Daisaku Katagiri, Warren J. Gross, Takahiro Hanyu. 59-64 [doi]
• A standard cell approach for MagnetoElastic NML circuitsDavide Giri, Marco Vacca, Giovanni Causapruno, Wenjing Rao, Mariagrazia Graziano, Maurizio Zamboni. 65-70 [doi]
• Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowiresNesrine Ben Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. R. Wang, Dafine Ravelosona. 71-76 [doi]
• n-to-n BCD priority encoderNusrat Jahan Lisa, Hafiz Md. Hasan Babu. 77-82 [doi]
• Memristor content addressable memoryWanlong Chen, Xiao Yang, Frank Zhigang Wang. 83-87 [doi]
• A tunable cache for approximate computingMagnus Själander, Nina Shariati Nilsson, Stefanos Kaxiras. 88-89 [doi]
• Robust sequence storage in bistable oscillatorsDavid Colliaux, Pierre Bessière, Jacques Droulez. 90-91 [doi]
• A CMOS-memristive self-learning neural network for pattern classification applicationsMelika Payvand, Justin Rofeh, Avantika Sodhi, Luke Theogarajan. 92-97 [doi]
• Sub-crosspoint RRAM decoding for improved area efficiencyRavi Patel, Eby G. Friedman. 98-103 [doi]
• Volatile memristive devices as short-term memory in a neuromorphic learning architectureJens Burger, Christof Teuscher. 104-109 [doi]
• Pipeline design in spintronic circuitsNickvash Kani, Azad Naeemi. 110-115 [doi]
• A model for variation- and fault-tolerant digital logic using self-assembled nanowire architecturesAlireza Goudarzi, Matthew R. Lakin, Darko Stefanovic, Christof Teuscher. 116-121 [doi]
• NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing techniqueNandakishor Yadav, Shikha Jain, Manisha Pattanaik, G. K. Sharma. 122-128 [doi]
• Molecular transistor circuits: From device model to circuit simulationAli Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini. 129-134 [doi]
• Monte Carlo simulations of carbon nanotube networks for optoelectronic applicationsMiguel Diez-Garcia, Adrien F. Vincent, Nicolas Izard, Damien Querlioz. 135-136 [doi]
• Hysteresis-free carbon nanotube field-effect transistors without passivationJ. Tittmann, S. Hermann, S. E. Schulz, A. Pacheco-Sanchez, M. Claus, M. Schroter, S. E. Schulz. 137-138 [doi]
• A low contact resistance graphene field effect transistor with single-layer-channel and multi-layer-contactHonghui Sun, Liang Fang, Yao Wang 0002, Yaqing Chi, Rulin Liu. 139-144 [doi]
• Floating-point unit design with nano-electro-mechanical (NEM) relaysSumit Dutta, Vladimir Stojanovic. 145-150 [doi]
• Energy effective 3D stacked hybrid NEMFET-CMOS cachesMihai Lefter, Marius Enachescu, George Razvan Voicu, Sorin Dan Cotofana. 151-156 [doi]
• Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selectionHassan Ghasemzadeh Mohammadi, Pierre-Emmanuel Gaillardon, Majid Yazdani, Giovanni De Micheli. 163-168 [doi]
• Stochastic reliability evaluation of Sea-of-Tiles based on Double Gate controllable-polarity FETsCatherine Dezan, Sara Zermani. 169-170 [doi]
• Wave-based multi-valued computation frameworkSantosh Khasanvis, Mostafizur Rahman, Sankara Narayanan Rajapandian, Csaba Andras Moritz. 171-176 [doi]
• Applications of wavelength-fan-in for high-performance distributed processing systemsAlexander N. Tait, Paul R. Prucnal. 177-178 [doi]
• Virtual prototyping of R2D NASIC based FPGACiprian Teodorov, Loïc Lagadec. 179-180 [doi]