Table of Contents

• System Level Policies for Fault Tolerance Issues in the FERMI ProjectA. Dell Acqua, M. Hansen, S. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, A. Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, S. Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson. 1-8
• Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC CodesR. Rochet, Régis Leveugle, Gabriele Saucier. 9-16
• Block Implementation of Fault-Tolerant LMS Adaptive FIR FiltersLiangkung Lin, G. Robert Redinbo. 17-24
• Fault-Tolerant Sorting Using VLSI Processor ArraysHee Yong Youn, Kyung Ook Lee. 25-32
• A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State DisksGian-Carlo Cardarilli, M. Di Zenzo, Pat O. Pistilli, Adelio Salsano. 33-40
• High Level Synthesis Techniques for Efficient Built-In-Self RepairLisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey. 41-48
• Detection of Defective Media in DisksHannu Kari, Heikki Saikkonen, Fabrizio Lombardi. 49-55
• A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional ArchitecturesHussain Al-Asaad, Elias S. Manolakos. 56-63
• On the Reconfiguration of Degradable VLSI/WSI ArraysChor Ping Low, Hon Wai Leong. 64-71
• Functional Testing and Reconfiguration of MIMD MachinesChouki Aktouf, Chantal Robach, Guy Mazaré, J. Johansson. 72-79
• A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to HypercubeHideo Ito. 80-87
• On the Reconfigurable Operation of Arrays with Defects for Image ProcessingJosé Salinas, Fabrizio Lombardi. 88-95
• Front-end Electronics in the Radiation Environment of LHCA. Kerek. 96-100
• Analysis of the Floating Gate Defect in CMOSVíctor H. Champac, Antonio Rubio, Joan Figueras. 101-108
• Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS DesignsAntonio Casimiro, M. Simões, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 109-116
• Fast Multi-Layer Critical Area ComputationHua Xue, Chennian Di, Jochen A. G. Jess. 117-124
• TEh Reliability of the Integrated Circuits in Automotive IndustryEnrico Ferrati, Magneti Marelli. 125-126
• A Logistic Regression Yield Model for SRAM Bit Fail PatternsRandall S. Collica. 127-135
• Yield Model for ASIC and Processor ChipsCharles H. Stapper, J. A. Patrick, R. J. Rosner. 136-143
• Some Results on Yield and Local Design Rule RelaxationJ. Crépeau, Claude Thibeault, Yvon Savaria. 144-151
• Use of a Segmentation Technique to Analyze the Variability of the Yield of a Mature CMOS SRAMFrederic Duvivier, M. Rivier, B. Burtschy, J. J. Charlot. 152-158
• Does the Floorplan of a Chip Affect Its Yield?Zahava Koren, Israel Koren. 159-166
• An Interactive Yield Estimator as a VLSI CAD ToolIsrael A. Wagner, Israel Koren. 167-174
• Topological Optimization of PLAs for Yield EnhancementVenkat K. R. Chiluvuri, Israel Koren. 175-182
• A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare AllocationEiji Fujiwara, Masaharu Tanaka. 183-190
• Fault Detection in Sequential Circuits through Functional TestingGiacomo Buonanno, Franco Fummi, Donatella Sciuto. 191-198
• Layout Level Design for Testability Strategy Applied to a CMOS Cell LibraryM. Rullán, F. C. Blom, J. Oliver, C. Ferrer. 199-206
• Current Testing Viability in Dynamic CMOS CircuitsMichel Renovell, Joan Figueras. 207-214
• Probabilistic Identification of Critical Components for Circuit DelaysDavid Wessels, Jon C. Muzio. 215-222
• Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal FeedbacksMassimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza. 223-230
• The T9000 Transputer: A Practical Example of the Application of Standard Test TechniquesGraham Frearson. 231-238
• Design of Self-Parity Combinational Circuits for Self-testing and On-line DetectionEgor S. Sogomonyan, Michael Gössel. 239-246
• Design and Implementation of a Merged On-Line and Off-Line Self Textable ArchitectureXiaoling Sun, Micaela Serra. 247-254
• Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor ArraysDah-Yea Wei, Jung Hwan Kim, T. R. N. Rao. 255-262
• A Probabilistic Measurement for Totally Self-Checking CircuitsJien-Chung Lo, Eiji Fujiwara. 263-270
• Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional BlockCecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò. 271-278
• A Highly Testable 1-out-of-3 CMOS CheckerCecilia Metra, Michele Favalli, Piero Olivo, Bruno Riccò. 279-286
• VLSI Concurrent Error Correcting Adders and MultipliersYuang-Ming Hsu, Earl E. Swartzlander Jr.. 287-294
• Functional Testing of Linear Circuits Using Transient Response AnalysisD. Taylor, P. S. A. Evans, D. Marland. 295-302
• Neural Networks for Multiple Fault Diagnosis in Analog CircuitsAlessandra Fanni, Alessandro Giua, Enrico Sandoli. 303-310
• Realistic Fault Analysis of CMOS Analog Building BlocksP. Nicolau, J. Barbosa, M. Saraiva, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira. 311-318
• Catastrophic Defects Oriented Testability Analysis of a Class AB AmplifierManoj Sachdev. 319-326
• Device Mismatch Limitations on the Performance of a Hamming Distance ClassifierNagendra Kumar, Philippe O. Pouliquen, Andreas G. Andreou. 327-334