Charles H. Stapper - researchr alias

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Viewing Publication 1 - 20 from 20

2000

LSI yield modeling and process monitoringCharles H. Stapper. ibmrd, 44(1):112-118, 2000. [doi]

1995

Multipurpose DRAM architecture for optimal power, performance, and product flexibilityWayne F. Ellis, John E. Barth Jr., Sri Divakaruni, Jeffrey Dreibelbis, Anatol Furman, Erik L. Hedberg, Hsing-San Lee, Thomas M. Maffitt, Christopher P. Miller, Charles H. Stapper, Howard L. Kalter. ibmrd, 39(1-2):51-62, 1995.

1994

A statistical study of defect maps of large area VLSI IC sIsrael Koren, Zahava Koren, Charles H. Stapper. tvlsi, 2(2):249-256, 1994. [doi]

On Fractal Yield Models: A Statistical ParadoxCharles H. Stapper, A. J. Rideout. dft 1994: 83-87

1993

A Unified Negative-Binomial Distribution for Yield Analysis of Defect-Tolerant CircuitsIsrael Koren, Zahava Koren, Charles H. Stapper. TC, 42(6):724-734, 1993.

Yield Model for ASIC and Processor ChipsCharles H. Stapper, J. A. Patrick, R. J. Rosner. dft 1993: 136-143

Improved Yield Models for Fault-Tolerant Memory ChipsCharles H. Stapper. TC, 42(7):872-881, 1993.

1992

A New Statistical Approach for Fault-Tolerant VLSI SystemsCharles H. Stapper. ftcs 1992: 356-365

Synergistic Fault-Tolerance for Memory ChipsCharles H. Stapper, Hsing-San Lee. TC, 41(9):1078-1087, 1992.

1991

High-speed on-chip ECC for synergistic fault-tolerance memory chipsJohn A. Fifield, Charles H. Stapper. jssc, 26(10):1449-1452, October 1991. [doi]

Statistics associated with spatial fault simulation used for evaluating integrated circuit yield enhancementCharles H. Stapper. tcad, 10(3):399-406, 1991. [doi]

1990

A 50-ns 16-Mb DRAM with a 10-ns data rate and on-chip ECCHoward L. Kalter, Charles H. Stapper, John E. Barth Jr., John DiLorenzo, Charles E. Drake, John A. Fifield, Gordon A. Kelley, Scott C. Lewis, Willem B. van der Hoeven, James A. Yankosky. jssc, 25(5):1118-1128, October 1990. [doi]

1989

Large-Area Fault Clusters and Fault Tolerance in VLSI Circuits: A ReviewCharles H. Stapper. ibmrd, 33(2):162-173, 1989.

Simulation of spatial fault distributions for integrated circuit yield estimationsCharles H. Stapper. tcad, 8(12):1314-1318, 1989. [doi]

1986

Yield of VLSI circuits: myths vs. reality (panel)Andrzej J. Strojwas, Clark Beck, Dennis Buss, Tülin Erdim Mangir, Charles H. Stapper. dac 1986: 234-235 [doi]

1984

Modeling of Defects in Integrated Circuit Photolithographic PatternsCharles H. Stapper. ibmrd, 28(4):461-475, 1984.

Yield Model for Fault Clusters Within Integrated CircuitsCharles H. Stapper. ibmrd, 28(5):636-640, 1984.

1983

Modeling of Integrated Circuit Defect SensitivitiesCharles H. Stapper. ibmrd, 27(6):549-557, 1983.

1980

Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good ProductCharles H. Stapper, A. N. McLaren, M. Dreckmann. ibmrd, 24(3):398-409, 1980. [doi]

1976

LSI Yield Modeling and Process MonitoringCharles H. Stapper. ibmrd, 20(3):228-234, 1976.

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