Abstract is missing.
- Scheduling Policies for Fault Tolerance in a VLSI ProcessorYinan N. Shen, Hannu Kari, S. S. Kim, Fabrizio Lombardi. 1-9
- A CMOS Fault Tolerant Architecture for Swith-Level FaultsCristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli. 10-18
- A Defect and Fault Tolerant Interconnection Network Strategy for WASP DevicesM. B. Alhaji-Hussaini, R. Mike Lea. 19-27
- Implementation of a Gracefully Degradable Binary Tree in ProgrammableS. Goldberg, Shambhu J. Upadhyaya. 28-36
- Fault-Tolerant Modular ConvolvesLuigi Dadda, Vincenzo Piuri. 37-45
- An Approach to the Development of a IDDQ Testable Cell LibraryC. Ferrer, D. Dateo, J. Oliver, Antonio Rubio, M. Rullán. 46-54
- Augmenting Scan Path SRLs with an XOR Network to Enhance Delay Fault TestingZaifu Zhang, Robert D. McLeod, Witold Pedrycz. 55-64
- On the Testability of CMOS Feedback AmplifiersA. J. Bishop, André Ivanov. 65-73 [doi]
- Roundoff Error-Free Tests in Algorithm-Based Fault Tolerant Matrix Operations on 2-D Processor ArraysDah-Yea Wei, Jung Hwan Kim, T. R. N. Rao. 74-82
- On Fractal Yield Models: A Statistical ParadoxCharles H. Stapper, A. J. Rideout. 83-87
- Efficient Critical Area Algorithms and Their Application to Yield Improvement and Test StrategiesGerard A. Allan, Anthony J. Walton. 88-96
- The Effect of Wire Length Minimization on YieldVenkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns. 97-105
- Laser Processes for Defect Correction in Large Area VLSI SystemsGlenn H. Chapman. 106-114
- Synthesis of Multi-level Self-Checking LogicFabio Salice, Mariagiovanna Sami, Donatella Sciuto. 115-123
- Design of Cover Circuits for Monitoring the Output of a MISAT. Bogue, Helmut Jürgensen, Michael Gössel. 124-132
- CMOS Self Checking Circuits with Faulty Sequential Functional BlockCecilia Metra, Michele Favalli, Bruno Riccò. 133-141
- Highly Testable and Compact 1-out-of-n CMOS CheckersCecilia Metra, Michele Favalli, Bruno Riccò. 142-150
- Some Results on Improving the Code Length of SbEC-DED CodesSihai Xiao, Xiaofa Shi, Guilang Feng, T. R. N. Rao. 151-158
- Reliability Estimation for Time Redundant Error Correcting Adders and MultipliersYuang-Ming Hsu, Earl E. Swartzlander Jr.. 159-167
- A Fault-Tolerant Associative Approach to On-Line Memory RepairJie-Chung Lo. 168-176
- Fault Tolerant Design Using Error Correcting Code for Multilayer Neural NetworksHideo Ito, Takashi Yagi. 177-184
- Defect and Fault Tolerant Scan ChainsRachid Kermouche, Yvon Savaria. 185-193
- Reconfiguration in 3D MeshesAnuj Chandra, Rami G. Melhem. 194-202
- On Soft Switch Programming for Reconfigurable Array SystemsTong Liu, Fabrizio Lombardi. 203-211
- A Self-Reconfiguration Architecture for Mesh ArraysSusumu Horiguchi, Issei Numata. 212-220
- A General Method to Design and Reconfigure Loop-Based Linear ArraysWeiping Shi. 221-229
- Statistical analysis of Particle/Defect Data Experiments Using Poisson and Logistic RegressionBrenda S. Cantell, Randall S. Collica, José G. Ramírez. 230-238
- A Yield Study of VLSI AddersZhan Chen, Israel Koren. 239-245
- Yield Enhancement with Particle Defects ReductionKiyoshi Mori, Nam T. Nguyen, Dewey Keeton, Ross Burns. 246-253
- Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural MethodFranco Fummi, Donatella Sciuto, Micaela Serra. 254-262
- On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital CircuitsAntonio Casimiro, F. Conçalves, João Paulo Teixeira, Marcelino B. Santos. 263-270
- Alternative Approaches to Fault Detection in FSMsRégis Leveugle, R. Rochet, Gabriele Saucier. 271-279
- Using Fourier Analysis to Enhance IC TestabilityClaude Thibeault. 280-298