Table of Contents

• Two Hardware Implementations for the Montgomery Modular Multiplication: Sequential versus ParallelNadia Nedjah, Luiza de Macedo Mourelle. 3-8 [doi]
• Analysis and Implementation of a Stochastic Multiplier for Electrical Power MeasurementAndré Borin Soares, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 9-13 [doi]
• A New Architecture for 2's Complement Gray Encoded Array MultiplierEduardo Costa 0001, Sergio Bampi, José Monteiro 0001. 14-19 [doi]
• Architectural Synthesis of Finite Impulse Response Digital FiltersRonald W. Mehler, Dian Zhou. 20-28 [doi]
• HW/SW Codesign of Handoff Protocol for Wireless ATM Networks Based on Performance Optimization Using Genetic AlgorithmRicardo N. B. Lima, Marcio N. Miranda, José V. S. Filho. 29-34 [doi]
• APU: Specification and Design of a Multi Algorithm ATM Policing Unit IPJosé Antônio Gomes de Lima, Antonio Carlos Cavalcanti, Solon Ferreira de Lucena. 35-42 [doi]
• Multithreaded Architectural Support for Speculative Trace Scheduling in VLIW ProcessorsManvi Agarwal, S. K. Nandy 0001, Jos T. J. van Eijndhoven, S. Balakrishanan. 43-48 [doi]
• A Novel Method for Improving the Operation Autonomy of SIMD Processing ElementsManuel Lois Anido, Alexander Paar, Nader Bagherzadeh. 49-56 [doi]
• An Integrated CMOS Instrumentation Amplifier with Improved CMRRPaulo Augusto Dal Fabbro, Carlos A. dos Reis Filho. 57-61 [doi]
• A Continuous-Time Incremental Analog to Digital ConverterRicardo Doldán, Alberto Yúfera, Adoración Rueda. 62-67 [doi]
• Capacitor Charge Control Technique Applied to Digitally Programmable IIR Switched-Capacitor FilterJoarez B. Monteiro, Antonio Petraglia, Carlos Azeredo Leme. 68-73 [doi]
• Analog Decimator IC in Direct-form Polyphase StructureJacqueline S. Pereira, Fernando A. P. Barúqui, Antonio Petraglia. 74-82 [doi]
• Testability Properties of BDDsFelipe S. Marques 0001, Vinícius P. Correia, A. Prado, Marcelo Lubaszewski, André Inácio Reis. 83-88 [doi]
• Reducing Test Application Time through Interleaved ScanFulvio Corno, Matteo Sonza Reorda, Giovanni Squillero. 89-94 [doi]
• Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular RedundancyRenato Fernandes Hentschke, Felipe S. Marques 0001, Fernanda Lima, Luigi Carro, Altamiro Amadeu Susin, Ricardo Reis 0001. 95-100 [doi]
• A Software Fault Tolerance Method for Safety-Critical Systems: Effectiveness and DrawbacksBogdan Nicolescu, Raoul Velazco, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante. 101-108 [doi]
• Interface Generation for Concurrent Processes During Hardware/Software Co-synthesisCristiano C. de Araújo, Edna Barros. 109-114 [doi]
• A Heterogeneous and Distributed Co-Simulation EnvironmentAlexandre M. Amory, Fernando Moraes 0001, Leandro A. Oliveira, Ney Calazans, Fabiano Hessel. 115-120 [doi]
• A Study on Communication Issues for Systems-on-ChipCesar A. Zeferino, Márcio Eduardo Kreutz, Luigi Carro, Altamiro Amadeu Susin. 121-126 [doi]
• A Study on a Garbage Collector for Embedded ApplicationsRafael C. Krapf, Júlio C. B. de Mattos, Gustavo Spellmeier, Luigi Carro. 127-134 [doi]
• A Noise Generator for Analog-to-Digital Converter TestingM. G. C. Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 135-140 [doi]
• A Statistical Sampler for Increasing Analog Circuits ObservabilityMarcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin. 141-148 [doi]
• A Methodology for Dynamic Power Consumption Estimation Using VHDL DescriptionsJoão M. S. Alcântara, Antônio C. C. Vieira, Federico Gálvez-Durand, Vladimir Castro Alves. 149-154 [doi]
• Power Consumption in Point-to-Point Interconnect ArchitecturesAlberto García Ortiz, Tudor Murgan, Leandro Soares Indrusiak, Manfred Glesner. 155-162 [doi]
• Collaborative Design Using a Shared Object Spaces InfrastructureSandro Sawicki, Lisane B. de Brisolara, Leandro S. lndrusiak, Ricardo Reis 0001. 163-168 [doi]
• Experiences on Analog Circuit Technology Migration and ReuseRaúl Acosta, Fernando Silveira, Pablo Aguirre. 169-176 [doi]
• Techniques and Mechanisms for Dynamic Reconfiguration in an Image ProcessorMarcos R. Boschetti, Alexandro M. S. Adário, Ivan Saraiva Silva, Sergio Bampi. 177-182 [doi]
• Core Communication Interface for FPGAsJosé Carlos S. Palma, Aline Vieira de Mello, Leandro Möller, Fernando Moraes 0001, Ney Calazans. 183-190 [doi]
• A Low-Cost FPGA Implementation of the Advanced Encryption Standard AlgorithmAnderson Cattelan Zigiotto, Roberto d'Amore. 191-196 [doi]
• An IP of an Advanced Encryption Standard for Altera" DevicesAlex Panato, Marcelo Barcelos, Ricardo Reis 0001. 197-202 [doi]
• Pipelined Entropy Coders for JPEG CompressionLuciano Volcan Agostini, Ivan Saraiva Silva, Sergio Bampi. 203-208 [doi]
• Signal Processing Applications for Embedded Java SystemsRafael C. Krapf, Júlio C. B. de Mattos, Gustavo Spellmeier, Luigi Carro. 209-216 [doi]
• Power Management Exploration for a Block Turbo DecoderJoão Martins, Marius Strum. 217-220 [doi]
• Low-Power Control Architecture for Embedded ProcessorsJúlio C. B. de Mattos, Márcio Eduardo Kreutz, Luigi Carro. 221-228 [doi]
• Exception Handling with Petri Net for Digital SystemsWagner Luiz Alves de Oliveira, Norian Marranghello, Furio Damiani. 229-234 [doi]
• CDFG -Petri Net Temporal Partitioning for Switching Context ApplicationsPaulo Sérgio B. do Nascimento, Manoel Eusebio de Lima, Paulo Maciel 0001. 235-242 [doi]
• An Offset Self-Correction Sample and Hold Circuit for Precise Applications in Low Voltage CMOSLuis Henrique de Carvalho Ferreira, Robson L. Moreno, Tales C. Pimenta, Carlos A. R. Filho. 243-246 [doi]
• Operational Amplifier Power Optimization for a Given Total (Slewing plus Linear) Settling TimeFernando Silveira, Denis Flandre. 247-253 [doi]
• A Switched-MOSFET Programmable Low-Voltage FilterLuís Cléber C. Marques, Wouter A. Serdijn, Carlos Galup-Montoro, Márcio C. Schneider. 254-257 [doi]
• Low-Voltage ADC for Sample to Serial Interface ApplicationsFathi A. Farag. 258-264 [doi]
• Automatic Generation of Digital Cell LibrariesJoão Daniel Togni, Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis. 265-270 [doi]
• A LEGAL Algorithm Following Global RoutingMarcelo de Oliveira Johann, Glauco Borges Valim dos Santos, Ricardo Augusto da Luz Reis. 271-276 [doi]
• Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path TracingGustavo Wilke, José Luís Güntzel, Márcio Bystronski, Ana Cristina M. Pinto, Ricardo Reis 0001. 277-282 [doi]
• Compression and Technology Mapping of Logic CircuitsVinícius Pazutti Correia, André Inácio Reis. 283-288 [doi]
• CMOS OTA Sizing Using ACM Model in a Graphical ApproachHenrique Costa de Moura Santos, Ana Isabela Araújo Cunha. 289-295 [doi]
• Design of Active Inductors Using CMOS TechnologyValdinei Luís Belini, M. A. Romero. 296-301 [doi]
• On Generating Compact, Passive Models of Frequency-Described SystemsCarlos P. Coelho, Joel R. Phillips, L. Miguel Silveira. 302-307 [doi]
• Behavioral Modeling of Analogue and Mixed Integrated Systems with VHDL-AMS for RF ApplicationsAhmed Fakhfakh, Hervé Levi, N. Milet-Lewis, Yves Danto. 308-316 [doi]
• On the Importance, Problems and Solutions of Pointer SynthesisNiels Vanspauwen, Edna Barros, Sérgio Cavalcante, Carlos Valderrama. 317-322 [doi]
• Requirements, Primitives and Models for Systems SpecificationCésar Augusto Missio Marcon, Ney Laert Vilar Calazans, Fernando Gehm Moraes. 323-330 [doi]
• System on a Chip for Petroleum Pipeline InspectionFábio da S. Dutra, Federico Gálvez-Durand, Vladimir Castro Alves. 331-336 [doi]
• Combined Turbo and Convolutional Decoder Architecture for UMTS Wireless ApplicationsGerd Kreiselmaier, Timo Vogt, Norbert Wehn, Friedbert Berens. 337-344 [doi]
• CMOS Bandgap with Base-Current Thermal CompensationJoão Paulo Cerquinho Cajueiro, Carlos A. dos Reis Filho. 345-349 [doi]
• A 4 Gsamples/S with 2-4 GHz Input Bandwidth SIGE Digitizer for Radio Astronomy ApplicationsDavid Deschans, Jean-Baptiste Bégueret, Yann Deval, Christophe Scarabello, Pascal Fouillat, Guy Montignac, Alain Baudry. 350-358 [doi]
• Minimizing the Number of Paths in BDDsGörschwin Fey, Rolf Drechsler. 359-364 [doi]
• Asynchronous Circuit Design Based on the RTBT Monostable-Bistable Logic Transition Element (MOBILE)Peter Glösekötter, Christian Pacha, Karl F. Goser, Werner Prost, Samuel O. Kim, Holger van Husen, Thorsten Reimann, Franz-Josef Tegude. 365-372 [doi]
• Data Transfer and Storage Exploration for Real-Time Implementation of a Digital Audio Broadcast Receiver on a Trimedia ProcessorMiguel Miranda, C. Ghez, Erik Brockmeyer, Pieter Op de Beeck, Francky Catthoor. 373-378 [doi]
• Configurable Systems-on-Chip (CSoC)Jürgen Becker 0001. 379-384 [doi]
• A Structural Test Methodology for SRAM-Based FPGAsMichel Renovell. 385 [doi]
• Ultra Low-Energy Transceivers for Wireless Sensor NetworksJan M. Rabaey. 386 [doi]
• Parametric Yield Estimation for Deep Sub- Micron VLSI CircuitsJochen A. G. Jess. 387 [doi]