Henrik Hulgaard - researchr alias

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Viewing Publication 1 - 26 from 26

2003

Satisfiability checking using Boolean Expression DiagramsPoul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard. STTT, 5(1):4-14, 2003. [doi]

2002

2001

Verification of Large State/Event Systems Using Compositionality and Dependency AnalysisJørn Lind-Nielsen, Henrik Reif Andersen, Henrik Hulgaard, Gerd Behrmann, Kåre J. Kristoffersen, Kim Guldstrand Larsen. fmsd, 18(1):5-23, 2001.

Satisfiability Checking Using Boolean Expression DiagramsPoul Frederick Williams, Henrik Reif Andersen, Henrik Hulgaard. TACAS 2001: 39-51 [doi]

2000

Symbolic timing analysis of asynchronous systemsHenrik Hulgaard, Tod Amon. tcad, 19(10):1093-1104, 2000. [doi]

Practical Verification of Embedded SoftwareJørgen Staunstrup, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen, Kim Guldstrand Larsen, Gerd Behrmann, Kåre J. Kristoffersen, Arne Skou, Henrik Leerberg, Niels Bo Theilgaard. Computer, 33(5):68-75, 2000. [doi]

1999

Symbolic Time Separation of EventsTod Amon, Henrik Hulgaard. async 1999: 83-93 [doi]

Verification of Hierarchical State/Event Systems Using Reusability and CompositionalityGerd Behrmann, Kim Guldstrand Larsen, Henrik Reif Andersen, Henrik Hulgaard, Jørn Lind-Nielsen. TACAS 1999: 163-177 [doi]

Equivalence checking of combinational circuits using Boolean expression diagramsHenrik Hulgaard, Poul Frederick Williams, Henrik Reif Andersen. tcad, 18(7):903-917, 1999. [doi]

Difference Decision DiagramsJesper B. Møller, Jakob Lichtenberg, Henrik Reif Andersen, Henrik Hulgaard. csl 1999: 111-125

Fully Symbolic Model Checking of Timed Systems using Difference Decision DiagramsJesper B. Møller, Jakob Lichtenberg, Henrik Reif Andersen, Henrik Hulgaard. ENTCS, 23(2):88-107, 1999. [doi]

Equivalence checking of hierarchical combinational circuitsPoul Frederick Williams, Henrik Hulgaard, Henrik Reif Andersen. icecsys 1999: 355-360 [doi]

1998

Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing ConstraintsFen Jin, Henrik Hulgaard, Eduard Cerny. FMCAD 1998: 167-184 [doi]

Verification of Large State/Event Systems Using Compositionality and Dependency AnalysisJørn Lind-Nielsen, Henrik Reif Andersen, Gerd Behrmann, Henrik Hulgaard, Kåre J. Kristoffersen, Kim Guldstrand Larsen. TACAS 1998: 201-216 [doi]

1997

Boolean Expression Diagrams (Extended Abstract)Henrik Reif Andersen, Henrik Hulgaard. lics 1997: 88-98 [doi]

Bounded Delay Timing Analysis of a Class of CSP ProgramsHenrik Hulgaard, Steven M. Burns. fmsd, 11(3):265-294, 1997.

1995

Efficient Timing Analysis of a Class of Petri NetsHenrik Hulgaard, Steven M. Burns. cav 1995: 423-436

An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent SystemsHenrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello. TC, 44(11):1306-1317, 1995. [doi]

Testing asynchronous circuits: A surveyHenrik Hulgaard, Steven M. Burns, Gaetano Borriello. integration, 19(3):111-131, 1995. [doi]

1994

Bounded delay timing analysis of a class of CSP programs with choiceHenrik Hulgaard, Steven M. Burns. async 1994: 2-11 [doi]

1993

An Algorithm for Exact Bounds on the Time Separation of Events in Concurrent SystemsTod Amon, Henrik Hulgaard, Steven M. Burns, Gaetano Borriello. iccd 1993: 166-173

Practical applications of an efficient time separation of events algorithmHenrik Hulgaard, Steven M. Burns, Tod Amon, Gaetano Borriello. iccad 1993: 146-151 [doi]

1991

Synthesizing Delay Insensitive Circuits from Verified ProgramsHenrik Hulgaard, Per H. Christensen, Jørgen Staunstrup. hlppp 1992: 326-337

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