Abstract is missing.
- Bounded delay timing analysis of a class of CSP programs with choiceHenrik Hulgaard, Steven M. Burns. 2-11 [doi]
- Tools for validating asynchronous digital circuitsAaron Ashkinazy, David A. Edwards, Craig Farnsworth, Gary Gendel, Shiv S. Sikand. 12-21 [doi]
- Timing-reliability evaluation of asynchronous circuits based on different delay modelsMasashi Kuwako, Takashi Nanya. 22-31 [doi]
- Sufficient conditions for correct gate-level speed-independent circuitsPeter A. Beerel, Jerry R. Burch, Teresa H. Y. Meng. 33-43 [doi]
- Characterizing speed-independence of high-level designsMichael Kishinevsky, Jørgen Staunstrup. 44-53 [doi]
- Retargeting a hardware compiler proof using protocol convertersGeoffrey Brown, Wayne Luk, John O'Leary. 54-63 [doi]
- Verification of the speed-independent circuits by STG unfoldingsAlex Kondratyev, Alexander Taubin. 64-75 [doi]
- How fast will the flip flop?Mark R. Greenstreet, Peter Cahoon. 77-86 [doi]
- Pipeline synchronizationJakov N. Seizovic. 87-96 [doi]
- Metastable-robust self-timed circuit synthesis from live safe simple signal transition graphsEdwin G. Y. Chung, Lindsay Kleeman. 97-105 [doi]
- Designing asynchronous circuits from behavioural specifications with internal conflictsJordi Cortadella, Luciano Lavagno, Peter Vanbekbergen, Alex Yakovlev. 106-115 [doi]
- Performance comparison of asynchronous addersMark A. Franklin, Tienyo Pan. 117-125 [doi]
- An asynchronous pipelined lattice structure filterUri Cummings, Andrew Lines, Alain J. Martin. 126-133 [doi]
- Building fast bundled data circuits with a specialized standard cell libraryPer Torstein Røine. 134-143 [doi]
- An event controlled reconfigurable multi-chip FFTShannon V. Morton, Sam S. Appleton, Michael J. Liebelt. 144-153 [doi]
- A delay-controlled phase-locked loop to reduce timing errors in synchronous/asynchronous communication linksJohn F. Chappel, Safwat G. Zaky. 156-165 [doi]
- A technique for estimating power in asynchronous circuitsPrabhakar Kudva, Venkatesh Akella. 166-175 [doi]
- Low-energy asynchronous memory designJosé A. Tierno, Alain J. Martin. 176-185 [doi]
- Utilising dynamic logic for low power consumption in asynchronous circuitsCraig Farnsworth, David A. Edwards, Shiv S. Sikand. 186-194 [doi]
- Efficient building blocks for delay insensitive circuitsPriyadarsan Patra, Donald S. Fussell. 196-205 [doi]
- Formal design of an asynchronous DSP counterflow pipeline: a case study in handshake algebraMark B. Josephs, Paul G. Lucassen, Jan Tijmen Udding, Tom Verhoeff. 206-215 [doi]
- Composable specifications for asynchronous systems using UNITYMark Bickford. 216-227 [doi]
- Delay-insensitive solutions to the committee problemIgor Benko, Jo C. Ebergen. 228-237 [doi]
- Testing micropipelinesAjay Khoche, Erik Brunvand. 239-246 [doi]
- Partial scan test for asynchronous circuits illustrated on a DCC error correctorMarly Roncken. 247-256 [doi]