Abstract is missing.
- Composable Template Attacks Using Templates for Individual Architectural ComponentsBozhi Liu, Roman Lysecky, Janet Meiling Wang Roveda. 1-8 [doi]
- Thermal-Aware 3D Symmetrical Buffered Clock Tree SynthesisDeok Keun Oh, Mu Jun Choi, Juho Kim. 9-16 [doi]
- Low-Overhead Microarchitectural Patching for Multicore Memory SubsystemsDoowon Lee, Opeoluwa Matthews, Valeria Bertacco. 17-25 [doi]
- Power Grab in Aggressively Provisioned Data Centers: What is the Risk and What Can Be Done About ItXiaofeng Hou, Luoyao Hao, Chao Li 0009, Quan Chen, Wenli Zheng, Minyi Guo. 26-34 [doi]
- Pensieve: a Machine Learning Assisted SSD Layer for Extending the LifetimeTe I, Murtuza Lokhandwala, Yu-Ching Hu, Hung-Wei Tseng. 35-42 [doi]
- Selective Compression Scheme for Read Performance Improvement on Flash DevicesQiao Li, Liang Shi, Riwei Pan, Cheng Ji, Xiaoqiang Li, Chun Jason Xue. 43-50 [doi]
- OSPADA: One-Shot Programming Aware Data Allocation Policy to Improve 3D NAND Flash Read PerformanceFei Wu 0005, Zuo Lu, You Zhou, Xubin He, Zhi-hu Tan, Changsheng Xie. 51-58 [doi]
- Cap: Exploiting Data Correlations to Improve the Performance and Endurance of SSD RAIDGaoxiang Xu, Zhipeng Tan, Dan Feng 0001, Yifeng Zhu, Xinyan Zhang, Jie Xu. 59-66 [doi]
- A Timing Side-Channel Attack on a Mobile GPUElmira Karimi, Zhen Hang Jiang, Yunsi Fei, David R. Kaeli. 67-74 [doi]
- Analysis of Row Hammer Attack on STTRAMMohammad Nasim Imtiaz Khan, Swaroop Ghosh. 75-82 [doi]
- Machine Learning on the Thermal Side-Channel: Analysis of Accelerator-Rich ArchitecturesDavid Werner, Kyle Juretus, Ioannis Savidis, Mark Hempstead. 83-91 [doi]
- CheriRTOS: A Capability Model for Embedded DevicesHongyan Xia, Jonathan Woodruff, Hadrien Barral, Lawrence Esswood, Alexandre Joannou, Robert Kovacsics, David Chisnall, Michael Roe, Brooks Davis, Edward Napierala, John Baldwin, Khilan Gudka, Peter G. Neumann, Alexander Richardson, Simon W. Moore, Robert N. M. Watson. 92-99 [doi]
- ReadPRO: Read Prioritization Scheduling in ORAM for Efficient Obfuscation in Main MemoriesJoydeep Rakshit, Kartik Mohanram. 100-107 [doi]
- SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave ExecutionWenjian He, Wei Zhang, Sanjeev Das, Yang Liu. 108-114 [doi]
- Breaking the Oblivious-RAM Bandwidth WallHamza Omar, Syed Kamran Haider, Ling Ren 0001, Marten van Dijk, Omer Khan. 115-122 [doi]
- Rearranging Random Issue Queue with High IPC and Short DelayShinji Sakai, Taishi Suenaga, Ryota Shioya, Hideki Ando. 123-131 [doi]
- Array Tracking Prefetcher for Indirect AccessesMustafa Cavus, Resit Sendag, Joshua J. Yi. 132-139 [doi]
- Dynamically Disabling Way-prediction to Reduce Instruction ReplayRicardo Alves, Stefanos Kaxiras, David Black-Schaffer. 140-143 [doi]
- Analysis and Characterization of Ultra Low Power Branch PredictorsAthanasios Chatzidimitriou, George Papadimitriou, Dimitris Gizopoulos, Shrikanth Ganapathy, John Kalamatianos. 144-147 [doi]
- OldSpot: A Pre-RTL Model for Fine-Grained Aging and Lifetime OptimizationAlec Roelke, Xinfei Guo, Mircea Stan. 148-151 [doi]
- SPF: Selective Pipeline FlushVignyan Reddy Kothinti Naresh, Rami Sheikh, Arthur Perais, Harold W. Cain. 152-155 [doi]
- Power-Efficient ReRAM-Aware CNN Model GenerationMaedeh Hemmat, Azadeh Davoodi. 156-162 [doi]
- R-Accelerator: A Reconfigurable Accelerator with RRAM Based Logic Contraction and Resource Optimization for Application Specific ComputingZhengyu Chen, Hai Zhou, Jie Gu. 163-170 [doi]
- 3D Crosspoint Memory as a Parallel Architecture for Computing Network ReachabilityAlvaro Velasquez, Sumit Kumar Jha 0001. 171-178 [doi]
- Dynamic Computing in Memory (DCIM) in Resistive Crossbar ArraysSeyedhamidreza Motaman, Swaroop Ghosh. 179-186 [doi]
- Low Area-Delay Complexity Digit-Level Parallel-In Serial-Out Multiplier Over GF(2m) Based on Overlap-Free Karatsuba AlgorithmChiou-Yng Lee, Jiafeng Xie. 187-194 [doi]
- Software and Hardware Techniques for Reducing the Impact of Quantization Errors in Memristor Crossbar ArraysBaogang Zhang, Rickard Ewetz. 195-201 [doi]
- Trading Off Temperature Guardbands via Adaptive ApproximationsBehzad Boroujerdian, Hussam Amrouch, Jörg Henkel, Andreas Gerstlauer. 202-209 [doi]
- Lattice-Traversing Design Space Exploration for High Level SynthesisLorenzo Ferretti, Giovanni Ansaloni, Laura Pozzi. 210-217 [doi]
- Heuristic Approximation of Early-Stage CNN Data Representation for Vision Intelligence SystemsJinhang Choi, Jack Sampson, Vijaykrishnan Narayanan. 218-225 [doi]
- Puppet: Energy Efficient Task Mapping For Storage-Less and Converter-Less Solar-Powered Non-Volatile Sensor NodesYue Xu, Hyung Gyu Lee, Xianzhang Chen, Bo Peng, Duo Liu, Liang Liang 0002. 226-233 [doi]
- SYNCVIBE: Fast and Secure Device Pairing through Physical Vibration on Commodity SmartphonesKyuin Lee, Vijay Raghunathan, Anand Raghunathan, Younghyun Kim. 234-241 [doi]
- FPGA Virtualization in Cloud-Based Infrastructures Over VirtioJoel Mandebi Mbongue, Festus Hategekimana, Danielle Tchuinkou Kwadjo, Christophe Bobda. 242-245 [doi]
- Forca: Fast and Atomic Remote Direct Access to Persistent MemoryHaixin Huang, Kaixin Huang, Litong You, Linpeng Huang. 246-249 [doi]
- CART: Cache Access Reordering Tree for Efficient Cache and Memory Accesses in GPUsYongbin Gu, Lizhong Chen. 250-257 [doi]
- ArchSampler: Architecture-Aware Memory Sampling Library for In-Memory ApplicationsJian Zhou, Jun Wang. 258-265 [doi]
- PIM-TGAN: A Processing-in-Memory Accelerator for Ternary Generative Adversarial NetworksAdnan Siraj Rakin, Shaahin Angizi, Zhezhi He, Deliang Fan. 266-273 [doi]
- Path Prefetching: Accelerating Index Searches for In-Memory DatabasesShuo Li, Zhiguang Chen, Nong Xiao, Guangyu Sun. 274-277 [doi]
- Reducing Inter-Application Interferences in Integrated CPU-GPU Heterogeneous ArchitectureHao Wen, Wei Zhang. 278-281 [doi]
- Solar-DRAM: Reducing DRAM Access Latency by Exploiting the Variation in Local BitlinesJeremie Kim, Minesh Patel, Hasan Hassan, Onur Mutlu. 282-291 [doi]
- Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA EngineAndreas Kurth, Pirmin Vogel, Andrea Marongiu, Luca Benini. 292-300 [doi]
- DR DRAM: Accelerating Memory-Read-Intensive ApplicationsYuhai Cao, Chao Li, Quan Chen 0002, Jingwen Leng, Minyi Guo, Jing Wang, Weigong Zhang. 301-309 [doi]
- Puzzle Memory: Multifractional Partitioned Heterogeneous Memory SchemeJee Ho Ryoo, Shuang Song, Lizy K. John. 310-317 [doi]
- Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking ApplicationsAndrew J. Douglass, Sunil P. Khatri. 318-325 [doi]
- Generalized Tree Architecture for Efficient Successive-Cancellation Polar DecodingHye-Yeon Yoon, Tae-Hwan Kim. 326-333 [doi]
- Parameterized Posit Arithmetic Hardware GeneratorRohit Chaurasiya, John Gustafson, Rahul Shrestha, Jonathan Neudorfer, Sangeeth Nambiar, Kaustav Niyogi, Farhad Merchant, Rainer Leupers. 334-341 [doi]
- BGIM: Bit-Grained Instant-on Memory Cell for Sleep Power Critical Mobile ApplicationsSoheil Salehi, Ronald F. DeMara. 342-345 [doi]
- Autonomous Temperature Management through Selective Control of Exact-Approximate TilesSiyuan Xu, Benjamin Carrión Schäfer. 346-349 [doi]
- Automatic Mapping of the Sum-Product Network Inference Problem to FPGA-Based AcceleratorsLukas Sommer, Julian Oppermann, Alejandro Molina 0001, Carsten Binnig, Kristian Kersting, Andreas Koch 0001. 350-357 [doi]
- BLPP: Improving the Performance of GPGPUs with Heterogeneous Memory through Bandwidth- and Latency-Aware Page PlacementKyu Yeun Kim, Woongki Baek. 358-365 [doi]
- General IDS Acceleration for High-Speed NetworksJan Kucera, Lukas Kekely, Adam Piecek, Jan Korenek. 366-373 [doi]
- Scalable Multi-Queue Data Transfer Scheme for FPGA-Based Multi-AcceleratorsSiavash Rezaei, Kanghee Kim, Eli Bozorgzadeh. 374-380 [doi]
- Characterizing 3D Charge Trap NAND Flash: Observations, Analyses and ApplicationsFei Wu 0005, Yue Zhu, Qin Xiong, Zhonghai Lu, You Zhou, Weizhen Kong, Changsheng Xie. 381-388 [doi]
- A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup AbilityKunal Bharathi, Harsh Kumar, Abbas Fairouz, Ahmad Al Kawam, Sunil P. Khatri. 389-396 [doi]
- Towards Efficient Microarchitecture Design of Simultaneous Localization and Mapping in Augmented Reality EraHuixiang Chen, Yuting Dai, Rui Xue, Kan Zhong, Tao Li. 397-404 [doi]
- Training Neural Networks with Low Precision Dynamic Fixed-PointSujeong Jo, Hanmin Park, Gunhee Lee, Kiyoung Choi. 405-408 [doi]
- Decentralized Collaborative Power Management through Multi-Device Knowledge SharingZhongyuan Tian, Haoran Li, Rafael Kioji Vivas Maeda, Jun Feng, Jiang Xu 0001. 409-412 [doi]
- Breeze: User-Level Access to Non-Volatile Main Memories for Legacy SoftwareAmirsaman Memaripour, Steven Swanson. 413-422 [doi]
- R-Cache: A Highly Set-Associative In-Package Cache Using Memristive ArraysPayman Behnam, Arjun Pal Chowdhury, Mahdi Nazm Bojnordi. 423-430 [doi]
- A Highly Non-Volatile Memory Scalable and Efficient File SystemFan Yang, Junbin Kang, Shuai Ma, Jinpeng Huai. 431-438 [doi]
- NVCool: When Non-Volatile Caches Meet Cold Boot AttacksXiang Pan, Anys Bacha, Spencer Rudolph, Li Zhou, Yinqian Zhang, Radu Teodorescu. 439-448 [doi]
- Guiding RTL Test Generation Using Relevant Potential InvariantsTania Khanna, Michael Hsiao. 449-455 [doi]
- Back-End Layout Reflection for Test Chip DesignZeye Liu, Ronald D. Blanton. 456-463 [doi]
- How Multi-Threshold Designs Can Protect Analog IPsAbdullah Ash-Saki, Swaroop Ghosh. 464-471 [doi]
- Optimization of Mutant Space for RTL Test GenerationKunal Bansal, Michael S. Hsiao. 472-475 [doi]
- A Reliability Study on CNNs for Critical Embedded SystemsMohamed Ayoub Neggaz, Ihsen Alouani, Pablo R. Lorenzo, Smaïl Niar. 476-479 [doi]
- DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCsYuechen Chen, Md Farhadur Reza, Ahmed Louri. 480-487 [doi]
- RETUNES: Reliable and Energy-Efficient Network-on-Chip ArchitecturePadmaja Bhamidipati, Avinash Karanth. 488-495 [doi]
- Accelerating Synchronization in Graph Analytics Using Moving Compute to Data Model on Tilera TILE-Gx72Halit Dogan, Masab Ahmad, Jose Joao, Omer Khan. 496-505 [doi]
- Eca-Router : On Achieving Endpoint Congestion Aware Switch Allocation in the On-Chip NetworkCunlu Li, Dezun Dong, Xiangke Liao. 506-509 [doi]
- Accurate Performance Bounds Calculation for Dynamic Voltage-Freq Islands in Best Effort NoCsDara Rahmati, Sobhan Masoudi, Ahmad Khonsari, Reza Sabbaghi-Nadooshan. 510-513 [doi]
- Design and Evaluation of a PVT Variation-Resistant TRNG CircuitBikash Poudel, Arslan Munir. 514-521 [doi]
- Hardware-Based Probabilistic Threat Detection and Estimation for Embedded SystemsNadir Amin Carreon, Sixing Lu, Roman Lysecky. 522-529 [doi]
- Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability CheckingSuyuan Chen, Ranga Vemuri. 530-536 [doi]
- Minimizing Thermal Variation in Heterogeneous HPC Systems with FPGA NodesYingyi Luo, Xiaoyang Wang, Seda Ogrenci Memik, Gokhan Memik, Kazutomo Yoshii, Peter H. Beckman. 537-544 [doi]
- A Compact AES Hardware Implementation Secure Against 1st-Order Side-Channel AttacksQian Zhang, Yongbin Zhou, Shuang Qiu 0004, Wei Cheng, Jingdian Ming, Rui Zhang. 545-552 [doi]
- PFCG: Improving the Restore Performance of Package Datasets in Deduplication SystemsChunxue Zuo, Fang Wang 0001, Ping Huang, Yuchong Hu, Dan Feng 0001, Yucheng Zhang. 553-560 [doi]
- OME: An Optimized Modeling Engine for Disk Failure Prediction in Heterogeneous DatacenterYanwen Xie, Dan Feng, Fang Wang, Xinyan Zhang, Jizhong Han, Xuehai Tang. 561-564 [doi]
- Enabling Accurate Performance Isolation on Hybrid Storage Devices in Cloud EnvironmentChuanwen Wang, Diansen Sun, Yunpeng Chai, Fang Zhou. 565-568 [doi]
- LEA: A Lazy Eviction Algorithm for SSD Cache in Cloud Block StorageKe Zhou 0001, Yu Zhang, Ping Huang, Hua Wang, Yongguang Ji, Bin Cheng, Ying Liu. 569-572 [doi]
- Optimizing Virtual Resource Management for Consolidated NUMA SystemsJianmin Qian, Jian Li, Ruhui Ma, Haibing Guan. 573-576 [doi]
- Fine-Grained Parallel Routing for FPGAs with Selective ExpansionMinghua Shen, Nong Xiao. 577-586 [doi]
- DEEP: Dedicated Energy-Efficient Approximation for Dynamically Reconfigurable ArchitecturesSiyuan Xu, Benjamin Carrión Schäfer. 587-594 [doi]
- Load Balance-Aware Multi-Core Parallel Routing for Large-Scale FPGAsMinghua Shen, Nong Xiao. 595-602 [doi]
- Using Machine Learning to Predict Path-Based Slack from Graph-Based Timing AnalysisAndrew B. Kahng, Uday Mallappa, Lawrence Saul. 603-612 [doi]