M. P. J. Stevens - researchr alias

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Viewing Publication 1 - 16 from 16

2003

A scalable single-chip multi-processor architecture with on-chip RTOS kernelBart D. Theelen, A. C. Verschueren, V. V. Reyes Suárez, M. P. J. Stevens, A. Nuñez. jsa, 49(12-15):619-639, 2003. [doi]

2002

Concurrent Support of Higher-Layer Protocols over WDMBart D. Theelen, Jeroen Voeten, P. H. A. van der Putten, M. P. J. Stevens, Harm J. S. Dorren. pnc, 4(1):47-62, 2002. [doi]

2001

Object-oriented modelling and specification using SHEMarc Geilen, Jeroen Voeten, P. H. A. van der Putten, Leo J. van Bokhoven, M. P. J. Stevens. Comp. Lang., Syst. \& Struct., 27(1/3):19-38, 2001.

1999

System Level Models for Real-Time CommunicationP. H. A. van der Putten, Jeroen Voeten, Marc Geilen, M. P. J. Stevens. euromicro 1999: 1496 [doi]

1998

System Level Modelling for Hardware/Software SystemsJeroen Voeten, P. H. A. van der Putten, Marc Geilen, M. P. J. Stevens. euromicro 1998: 10154-10161 [doi]

1997

Design-For-Debug in Hardware/Software Co-DesignHarald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers. codes 1997: 35-42 [doi]

1996

Behaviour-Preserving Transformations in SHE: A Formal Approach to Architecture DesignJeroen Voeten, P. H. A. van der Putten, M. P. J. Stevens. euromicro 1996: 19-27 [doi]

1994

System-Level Testability of Hardware/Software SystemsHarald P. E. Vranken, M. P. J. Stevens, M. T. M. Segers, J. H. M. M. van Rhee. itc 1994: 134-142

1993

TL: A system specification systemL. P. M. Benders, M. P. J. Stevens. jsa, 38(1-5):835-842, 1993. [doi]

1992

Task level specification and communicationL. P. M. Benders, M. P. J. Stevens. jsa, 35(1-5):355-362, 1992. [doi]

1991

Task level behavioral hardware descriptionL. P. M. Benders, M. P. J. Stevens. jsa, 32(1-5):323-331, 1991. [doi]

Object oriented system analysis for VLSIYun-Chao Hu, Ad Verschueren, M. P. J. Stevens. jsa, 32(1-5):101-108, 1991. [doi]

Compilation techniques for a high level language processorB. W. Watson, Willem J. Withagen, M. P. J. Stevens. jsa, 32(1-5):29-36, 1991. [doi]

1990

Designing high performance instruction caches in VLSIJ. E. H. M. Bormans, Willem J. Withagen, F. P. M. Budzelaar, M. P. J. Stevens. jsa, 30(1-5):135-142, 1990. [doi]

Pipelining a memory based CISC processorJ. P. C. F. H. Smeets, W. J. Withagen, M. P. J. Stevens. jsa, 30(1-5):665-672, 1990. [doi]

System level VLSI designM. P. J. Stevens, F. P. M. Budzelaar. jsa, 30(1-5):321-329, 1990. [doi]

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