Abstract is missing.
- Quality-Driven Decision Making Methodology for System-Level DesignLech Józwiak, Sien-An Ong. 8-18 [doi]
- Behaviour-Preserving Transformations in SHE: A Formal Approach to Architecture DesignJeroen Voeten, P. H. A. van der Putten, M. P. J. Stevens. 19-27 [doi]
- Considering Test Economics in the Process of Hardware/Software PartitioningGhassan Al Hayek, Yves Le Traon, Chantal Robach. 28 [doi]
- Increasing the Effective Memory Bandwidth in Multivector ProcessorsA. M. del Corral, José M. Llabería. 38-45 [doi]
- Implementation of Processor Cells for Array Algorithms on FPGAsIstván Vassányi, István Erényi. 46-50 [doi]
- Mapping of Neural Networks onto Data Flow GraphsAziz Can Yuceturk, Bernd Klauer, Stefan Zickenheiner, Ronald Moore, Klaus Waldschmidt. 51 [doi]
- A Comprehensive Approach in Performance Evaluation for Modern Real-Time Operating SystemsAlberto García-Martínez, Jesús Fernández-Conde, Ángel Viña. 61-68 [doi]
- An Algorithm for Scheduling Prioritized Tasks in a Hard Real-Time EnvironmentJoshua Etkin, José Fridman. 69-76 [doi]
- A Formal Design and Implementation Method for Real-Time Embedded SystemsSteven Bradley, William Henderson, David Kendall, Adrian Robson, Stephen Hawkes. 77 [doi]
- A Design Assistant for Scheduling of Design DecisionsReinhard Rauscher. 88-95 [doi]
- A Novel Circuit Extraction Tool Based on X-Spans and Y-SpansJoão M. S. Alcântara, C. E. T. Oliveira, Manuel L. Anido. 96-103 [doi]
- Automating System-Level Design: From Specification to ArchitectureKarlheinz Agsteiner, Dieter Monjau, Sören Schulze. 104 [doi]
- Effective SIMD Code Generation for the High-Level Declarative Data-Parallel Language 8 1/2Dominique De Vito, Olivier Michel. 114-119 [doi]
- Optimising Pseudoknotin FCMCGenésio Gomes da Cruz Neto, Ricardo Massa Ferreira Lima, Rafael Dueire Lins, André L. M. Santos. 120-126 [doi]
- Application of the V-Ray Technology for Optimization of the TRFD and FL052 Perfect Club Benchmarks to CRAY Y-MP and CRAY T3D SupercomputersAlexander S. Antonov, Vladimir V. Voevodin. 127 [doi]
- A Macro Expansion Approach to Embedded Processor Code GenerationEero Lassila. 136-142 [doi]
- Functional Validation of Fault-Tolerant Asynchronous AlgorithmsJan Hlavicka, Stanislav Racek, Pavel Smrha. 143-150 [doi]
- A Prototyping Technique with an Asychronous Specification LanguageMiroslav Svéda. 151-157 [doi]
- Software Engineering in Control Using Objects and ServicesOliver Hammerschmidt, Thomas Doersam. 158 [doi]
- A Semantic Model of VHDL for Validating Rewriting AlgebrasSheetanshu L. Pandey, Kothanda R. Subramanian, Philip A. Wilsey. 167-176 [doi]
- A Graph Rewriting Approach for Transformational Design of Digital SystemsCorrie Huijs. 177-184 [doi]
- Automatic Parallelization of a Petri Net-Based Design Representation for High-Level SynthesisPeter Grün, Petru Eles, Krzysztof Kuchcinski, Zebo Peng. 185-192 [doi]
- Reachability and Timing Analysis in Data Flow Networks: A Case StudyB. Antal, György Csertán, István Majzik, Andrea Bondavalli, Luca Simoncini. 193 [doi]
- Efficient Simulation of Multiprocessors through Finite State MachinesChristoph Siegelin, Ciaran O Donnell, Ulrich Finger. 202-206 [doi]
- A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus MultiprocessorsRoberto Giorgi, Cosimo Antonio Prete, Luigi M. Ricciardi, Gianpaolo Prina. 207-214 [doi]
- A Novel Approach to Improve the Performance of Interconnection Networks with Hot - SpotsJosé M. García, A. Flores. 215-222 [doi]
- A Load Balancing System for Windows NT NetworksLeszek Borzemski, Arkadiusz Kieda. 223 [doi]
- A General Framework for Positioning, Evaluating and Selecting the New Generation of Development ToolsJan Vanthienen, Stephan Poelmans. 233-241 [doi]
- A Multi-Agent Environment for User Interface DesignCecilia Inés Sosa Arias, Beatriz Mascia Daltrini. 242-247 [doi]
- Separating Application Functionality from the User Interface in a Distributed EnvironmentNomusa Dlodlo, Carl Bamford. 248 [doi]
- Results Given by a New Evaluation System for Placement and Routing HeuristicsReinhard Rauscher, Dieter Klawan, Hans-Jürgen Bandelt. 259-266 [doi]
- A System for Heuristic Modifications on PLA - SpecificationsReinhard Rauscher, Andreas Krause. 267-274 [doi]
- Retiming for Circuits with Enable RegistersHans-Georg Martin. 275 [doi]
- Transparency in a Replicated Network File SystemCharles Changli Chin, Shang-Rong Tsai. 285-291 [doi]
- Recovery Blocks and Algorithm-Based Fault ToleranceAndrew M. Tyrrell. 292 [doi]
- Communication Mechanism Independent Protocol Specification Based on CSP: A Case StudyYong Sun, Hongji Yang. 303-310 [doi]
- Software Monitoring and Debugging Using Compressed Signature SequencesIstván Majzik. 311-318 [doi]
- Preliminary Analysis Cycle for B-Method Software DevelopmentSouâd Taouil-Traverson, Sylvie Vignes. 319 [doi]
- Pseudorandom versus Deterministic Testing of Intel 80x86 ProcessorsJanusz Sosnowski, A. Kusmierczyk. 329-336 [doi]
- On the Adequacy of Deriving Hardware Test Data from the Behavioral SpecificationGhassan Al Hayek, Chantal Robach. 337-342 [doi]
- DELFIM: Error Detection by Thin Memory ProtectionJoão Carlos Cunha, João Gabriel Silva. 343-350 [doi]
- SCAN/BIST Techniques for Decreasing Test Storage and their implications to Test Pattern GenerationRoberto Bevacqua, Luca Guerrazzi, Franco Fummi. 351 [doi]
- N-Version Programming: A Unified Modeling ApproachKaterina Goseva-Popstojanova, Aksenti Grnarov. 363-370 [doi]
- Performance Evaluation of Testing Strategies in Parallel SystemsOum-El-Kheir Benkahla, F. Chevassu, B. Remy, Chantal Robach. 371-378 [doi]
- Effective Approximate Fault Diagnosis of Systems with Inhomogeneous Test InvalidationTamás Bartha. 379 [doi]
- Performance Analysis of Packet Switching Interconnection Networks with Finite BuffersAristotel Tentov, Aksenti L. Grnarov. 390-396 [doi]
- Multicast Routing Algorithms for Manhattan Street NetworkHoyoung Hwang, Hyoungjun Kim, Yanghee Choi, Chongsang Kim. 397-404 [doi]
- Performance Comparison of Experimented Switching Architectures for ATMPertti Raatikainen, Teleste Oy, Juha Zidbeck. 405-411 [doi]
- Connection Rerouting Method for General Application to Connection-Oriented Mobile Communication Net worksMinho Song, Yanghee Choi, Chongsang Kim. 412 [doi]
- Design and Performance of a Main Memory Hardware Data CompressorMorten Kjelsø, Mark Gooch, Simon Jones. 423-430 [doi]
- Performance Assessment of Contents Management in Multilevel On-Chip CachesPablo Ibáñez, Víctor Viñals. 431-440 [doi]
- Using Method Lookup Caches and Register Windowing to Speed Up Dynamically-Bound Object-Oriented ApplicationsKanad Ghose, Kiran Raghavendra Desai, Peter M. Kogge. 441 [doi]
- Comparing Performances and Quality of Service of Group Communication ProtocolsElena Pagani, Gian Paolo Rossi. 451-458 [doi]
- Experience of Adaptive Replication in Distributed File SystemsGiacomo Cabri, Antonio Corradi, Franco Zambonelli. 459-466 [doi]
- A New Control Service Model Based on CORBA for Distributed Multimedia ObjectsHan-Suk Choi, Jae Soo Yoo, Ok-Bae Chang. 467 [doi]
- Hardware/Software Co-Design of Communication ProtocolsStefan Fischer, Jacek Wytrebowicz, Stanislaw Budkowski. 476-483 [doi]
- Formal Specification of Communication Protocols Based on a Timed-SDL: Validation and Performance ProspectsChie Dou. 484-491 [doi]
- Formal Specification of Communication Protocols with Object-Based ECATNetsMohamed Bettaz, Mourad Maouche, Kamel Barkaoui. 492 [doi]
- The Design of a Specialised Processor for the Simulation of Sintering A. PostulaAdam Postula, David Abramson, Paul Logothetis. 501-508 [doi]
- Real-Time Scheduling Co-Processor in Hardware for Single and Multiprocessor SystemsJohan Stärner, Joakirn Adomat, John Furunäs, Lennart Lindh. 509-512 [doi]
- Design of a Hybrid Digital-Analog Neural Co-Processor for Signal ProcessingAlexandre R. S. Romariz, P. U. A. Ferreira, J. V. Campêlo Jr., M. L. Graciano Jr., J. C. da Costa. 513-519 [doi]
- An FPGA-Based Square-Root Co-ProcessorV. Tchoumatchenko, T. Vassileva, P. Gurov. 520 [doi]
- Parallel Set Operations with Visual DataPetr Zemánek. 529-536 [doi]
- Parallel Approaches to the Segmentation of Free-Hand DrawingsRichard Canham, Stephen L. Smith, Andrew M. Tyrrell. 537 [doi]
- Efficient Program Composition on Parix by the Ensemble MethodologyJohn Yiannis Cotronis. 545-552 [doi]
- Paradigms for Parallel Dynamic ProgrammingCasiano Rodríguez, José L. Roda, F. García, Francisco Almeida, Daniel González. 553 [doi]
- The Design and Implementation of a Multimedia Storage Server to Support Video-on-Demand ApplicationsAnastasio Molano, Alberto García-Martínez, Ángel Viña. 564-571 [doi]
- Architecture and Implementation for Scalable Transfer of Live Videos in Multimedia ApplicationsRobert Hess, Tino Hutschenreuther, Ralf Lehmann, Alexander Schill. 572-580 [doi]
- Automatic Scheduling of Applications with Temporal QoS Constraints: A Case StudyJocelyne Farhat-Gissler, Isabelle M. Demeure. 581 [doi]
- Towards Extremely Fast Context Switching in a Block-Multithreaded ProcessorWinfried Grünewald, Theo Ungerer. 592-599 [doi]
- Low-Power Embedded Microprocessor DesignChristian Piguet, T. Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers. 600-605 [doi]
- A Fast Capability Extension to a RISC ArchitectureKanad Ghose, Pavel Vasek. 606 [doi]
- Broadcast with Time and Causality Constraints for Multimedia ApplicationsRoberto Baldoni, Michel Raynal, Ravi Prakash, Mukesh Singhal. 617-624 [doi]
- Causal Modeling of a Video-on-Demand System Using Predicate/Transition Net FormalismTino Pyssysalo, Leo Ojala. 625-632 [doi]
- Statistical Admission Control in Video Servers with Variable Bit-Rate Streams and Constant Time Length RetrievaErnst Biersack, Frédéric Thiesse. 633 [doi]
- Instruction Scheduling for a Superscalar ArchitectureRoger Collins, Gordon Steven. 643-650 [doi]
- Load Balancing in Superscalar ArchitecturesEliseu M. Chaves Filho, Edil S. Tavares Fernandes, Andrew Wolfe. 651 [doi]