Abstract is missing.
- Technology and design challenges for mobile communication and computing productsDennis Buss. 1 [doi]
- FinFET-based SRAM designZheng Guo, Sriram Balasubramanian, Radu Zlatanovici, Tsu-Jae King, Borivoje Nikolic. 2-7 [doi]
- Modeling and analysis of total leakage currents in nanoscale double gate devices and circuitsSaibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy. 8-13 [doi]
- Effectiveness of low power dual-V::t:: designs in nano-scale technologies under process parameter variationsAmit Agarwal, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy. 14-19 [doi]
- Analysis and mitigation of variability in subthreshold designBo Zhai, Scott Hanson, David Blaauw, Dennis Sylvester. 20-25 [doi]
- Measurements and modeling of intrinsic fluctuations in MOSFET threshold voltageAli Keshavarzi, Gerhard Schrom, Stephen Tang, Sean Ma, Keith A. Bowman, Sunit Tyagi, Kevin Zhang, Tom Linton, Nagib Hakim, Steven G. Duvall, John Brews, Vivek De. 26-29 [doi]
- Instruction packing: reducing power and delay of the dynamic scheduling logicJoseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin. 30-35 [doi]
- Energy-efficient and high-performance instruction fetch using a block-aware ISAAhmad Zmily, Christos Kozyrakis. 36-41 [doi]
- Energy-aware fetch mechanism: trace cache and BTB customizationDaniel Chaver, Miguel A. Rojas, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang. 42-47 [doi]
- Understanding the energy efficiency of SMT and CMP with multiclusteringJason Cong, Ashok Jagannathan, Glenn Reinman, Yuval Tamir. 48-53 [doi]
- A simple mechanism to adapt leakage-control policies to temperatureStefanos Kaxiras, Polychronis Xekalakis, Georgios Keramidas. 54-59 [doi]
- A 120nm low power asynchronous ADCEmmanuel Allier, Julien Goulier, Gilles Sicard, A. Dezzani, Eric André, Marc Renaudin. 60-65 [doi]
- A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13µm CMOSXinhua Chen, Qiuting Huang. 66-71 [doi]
- A low power current steering digital to analog converter in 0.18 Micron CMOSDouglas Mercer. 72-77 [doi]
- Systematic power reduction and performance analysis of mismatch limited ADC designsPeter C. S. Scholtens, David Smola, Maarten Vertregt. 78-83 [doi]
- A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applicationsLucas Andrew Milner, Gabriel A. Rincón-Mora. 84-89 [doi]
- Challenges and opportunities for low power FPGAs in nanometer technologiesLei He, Mike Hutton, Tim Tuan, Steven J. E. Wilton. 90 [doi]
- A GHz-class charge recovery logicVisvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler. 91-94 [doi]
- Low-power fanout optimization using multiple threshold voltage invertersBehnam Amelifard, Farzan Fallah, Massoud Pedram. 95-98 [doi]
- A low-power bus design using joint repeater insertion and codingSrinivasa R. Sridhara, Naresh R. Shanbhag. 99-102 [doi]
- An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOSSteven Hsu, Amit Agarwal, Kaushik Roy, Ram Krishnamurthy, Shekhar Y. Borkar. 103-106 [doi]
- A low-power, multichannel gated oscillator-based CDR for short-haul applicationsArmin Tajalli, Paul Muller, Seyed Mojtaba Atarodi, Yusuf Leblebici. 107-110 [doi]
- An algebraic decision diagram (ADD) based technique to find leakage histograms of combinational designsKanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri. 111-114 [doi]
- Cascaded carry-select adder (C:::2:::SA): a new structure for low-power CSA designYiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh. 115-118 [doi]
- Region-level approximate computation reuse for power reduction in multimedia applicationsXueqi Cheng, Michael S. Hsiao. 119-122 [doi]
- Joint exploration of architectural and physical design spaces with thermal considerationYen-Wei Wu, Chia-Lin Yang, Ping-Hung Yuh, Yao-Wen Chang. 123-126 [doi]
- Coordinated, distributed, formal energy management of chip multiprocessorsPhilo Juang, Qiang Wu, Li-Shiuan Peh, Margaret Martonosi, Douglas W. Clark. 127-130 [doi]
- A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variationsVineet Wason, Kaustav Banerjee. 131-136 [doi]
- Power-optimal repeater insertion considering Vdd and Vth as design freedomsYu Ching Chang, King Ho Tam, Lei He. 137-142 [doi]
- Probabilistic dual-Vth leakage optimization under variabilityAzadeh Davoodi, Ankur Srivastava. 143-148 [doi]
- Linear programming for sizing, V::th:: and V::dd:: assignmentDavid G. Chinnery, Kurt Keutzer. 149-154 [doi]
- An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding designKuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Yuan-Sun Chu, Jiun-In Guo. 155-160 [doi]
- Cost-effective low-power processor-in-memory-based reconfigurable datapath for multimedia applicationsMarco Lanuzza, Martin Margala, Pasquale Corsonello. 161-166 [doi]
- Two efficient methods to reduce power and testing timeIl-soo Lee, Tony Ambler. 167-172 [doi]
- Power and thermal effects of SRAM vs. Latch-Mux design styles and clock gating choicesYingmin Li, Mark Hempstead, Patrick Mauro, David Brooks, Zhigang Hu, Kevin Skadron. 173-178 [doi]
- Complexity reduction in an nRERL microprocessorSeokkee Kim, Soo-Ik Chae. 180-185 [doi]
- Driver pre-emphasis techniques for on-chip global busesLiang Zhang, John Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon. 186-191 [doi]
- Multi-story power delivery for supply noise reduction and low voltage operationJie Gu, Chris H. Kim. 192-197 [doi]
- Low power SRAM techniques for handheld productsRabiul Islam, Adam Brand, Dave Lippincott. 198-202 [doi]
- High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolarMasaya Sumita. 203-208 [doi]
- An evaluation of code and data optimizations in the context of disk power reductionMahmut T. Kandemir, Seung Woo Son, Guangyu Chen. 209-214 [doi]
- Optimizing sensor movement planning for energy efficiencyGuiling Wang, Mary Jane Irwin, Piotr Berman, Haoying Fu, Thomas F. La Porta. 215-220 [doi]
- Power prediction for intel XScale processors using performance monitoring unit eventsGilberto Contreras, Margaret Martonosi. 221-226 [doi]
- Power reduction by varying sampling rateWilliam R. Dieter, Srabosti Datta, Wong Key Kai. 227-232 [doi]
- Energy efficient strategies for deployment of a two-level wireless sensor networkAli Iranli, Morteza Maleki, Massoud Pedram. 233-238 [doi]
- Power grid voltage integrity verificationMaha Nizam, Farid N. Najm, Anirudh Devgan. 239-244 [doi]
- The need for a full-chip and package thermal model for thermally optimized IC designsWei Huang, Eric Humenay, Kevin Skadron, Mircea R. Stan. 245-250 [doi]
- Peak temperature control and leakage reduction during binding in high level synthesisRajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik. 251-256 [doi]
- LAP: a logic activity packing methodology for leakage power-tolerant FPGAsHassan Hassan, Mohab Anis, Mohamed I. Elmasry. 257-262 [doi]
- Defocus-aware leakage estimation and controlAndrew B. Kahng, Swamy Muddu, Puneet Sharma. 263-268 [doi]
- Hierarchical power management with application to schedulingPeng Rong, Massoud Pedram. 269-274 [doi]
- Runtime identification of microprocessor energy saving opportunitiesW. L. Bircher, M. Valluri, J. Law, L. K. John. 275-280 [doi]
- Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancyAlireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Hashimi, Seyed Ghassem Miremadi, Paul M. Rosinger. 281-286 [doi]
- Bounds on power savings using runtime dynamic voltage scaling: an exact algorithm and a linear-time heuristic approximationFen Xie, Margaret Martonosi, Sharad Malik. 287-292 [doi]
- Power-aware code scheduling for clusters of active disksSeung Woo Son, Guangyu Chen, Mahmut T. Kandemir. 293-298 [doi]
- Wearable computing: a catalyst for business and entertainmentChandra Narayanaswami. 302 [doi]
- Design and optimization on dynamic power system for self-powered integrated wireless sensing nodesDongsheng Ma, Janet Meiling Wang, Mohankumar N. Somasundaram, Zongqi Hu. 303-306 [doi]
- Accurate battery lifetime estimation using high-frequency power profile emulationFarhan Simjee, Pai H. Chou. 307-310 [doi]
- On-chip digital power supply control for system-on-chip applicationsMaurice Meijer, José Pineda de Gyvez, Ralph Otten. 311-314 [doi]
- Self-timed circuits for energy harvesting AC power suppliesJeff Siebert, Jamie Collier, Rajeevan Amirtharajah. 315-318 [doi]
- A tunable bus encoder for off-chip data busesDinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar. 319-322 [doi]
- Fast configurable-cache tuning with a unified second-level cacheAnn Gordon-Ross, Frank Vahid, Nikil D. Dutt. 323-326 [doi]
- Dataflow analysis for energy-efficient scratch-pad memory managementGuangyu Chen, Mahmut T. Kandemir. 327-330 [doi]
- Energy reduction in multiprocessor systems using transactional memoryTali Moreshet, R. Iris Bahar, Maurice Herlihy. 331-334 [doi]
- Inter-program optimizations for conserving disk energyJerry Hom, Ulrich Kremer. 335-338 [doi]
- PARE: a power-aware hardware data prefetching engineYao Guo, Mahmoud Ben Naser, Csaba Andras Moritz. 339-344 [doi]
- Snug set-associative caches: reducing leakage power while improving performanceJia-Jhe Li, Yuan-Shin Hwang. 345-350 [doi]
- An energy efficient TLB design methodologyDongrui Fan, Zhimin Tang, Hailin Huang, Guang R. Gao. 351-356 [doi]
- Synonymous address compaction for energy reduction in data TLBChinnakrishnan S. Ballapuram, Hsien-Hsin S. Lee, Milos Prvulovic. 357-362 [doi]
- A non-uniform cache architecture for low power system designTohru Ishihara, Farzan Fallah. 363-368 [doi]
- Replacing global wires with an on-chip network: a power analysisSeongmoo Heo, Krste Asanovic. 369-374 [doi]
- A low-power crossroad switch architecture and its core placement for network-on-chipKuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen. 375-380 [doi]
- System level power and performance modeling of GALS point-to-point communication interfacesKoushik Niyogi, Diana Marculescu. 381-386 [doi]
- A technique for low energy mapping and routing in network-on-chip architecturesKrishnan Srinivasan, Karam S. Chatha. 387-392 [doi]
- Improving energy efficiency by making DRAM less randomly accessedHai Huang, Kang G. Shin, Charles Lefurgy, Tom W. Keller. 393-398 [doi]