Mark C. Johnson - researchr alias

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Viewing Publication 1 - 15 from 15

2021

Modeling and Circuit Analysis of Interconnects with TaS2 Barrier/LinerXinkang Chen, Chun-Li Lo, Mark C. Johnson, Zhihong Chen, Sumeet Kumar Gupta. drc 2021: 1-2 [doi]

2019

System-on-a-Chip Design as a Platform for Teaching Design and Design Flow IntegrationJacob Covey, Mark C. Johnson. glvlsi 2019: 249-253 [doi]

2017

Indiana bicentennial torch project: Trial by fireTodd Wild, Noah Chesnut, Gabriel Martini, Mark C. Johnson. mse 2017: 19-22 [doi]

2016

Student use and assessment of System on Chip (SOC) prototyping resourceMatthew Leiter, Lucas Goedde, Emily Fredette, Noah Chesnut, Matthew A. Swabey, Mark C. Johnson. ewme 2016: 1-4 [doi]

2011

Interactive application for learning RTL code structuresMark C. Johnson. mse 2011: 122-125 [doi]

2009

Undergraduate dual-core prototyping and analysis of factors influencing student success on dual-core designsMark C. Johnson, Eric P. Villasenor, Olga Krachina, Mithuna Thottethodi. mse 2009: 1-4 [doi]

2004

Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned FloorplanDongku Kang, Mark C. Johnson, Kaushik Roy. isqed 2004: 98-103 [doi]

2003

Multiple-Vdd Scheduling/Allocation for Partitioned FloorplanDongku Kang, Mark C. Johnson, Kaushik Roy. iccd 2003: 412-418 [doi]

2002

Leakage control with efficient use of transistor stacks in single threshold CMOSMark C. Johnson, Dinesh Somasekhar, Lih-Yih Chiou, Kaushik Roy. tvlsi, 10(1):1-5, 2002. [doi]

2001

igital Design Education Infrastructure Using Multiple EDA Tool Vendors and Multiple Modes of Tool AccessMark C. Johnson. mse 2001: 81-82 [doi]

1999

1997

Datapath scheduling with multiple supply voltages and level convertersMark C. Johnson, Kaushik Roy. todaes, 2(3):227-248, 1997. [doi]

1996

Optimal Selection of Supply Voltages and Level Conversions During Data Path Scheduling Under Resource ConstraintsMark C. Johnson, Kaushik Roy. iccd 1996: 72-77 [doi]

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