Abstract is missing.
- Microarchitecture in the system-level integration eraCharles R. Moore. [doi]
- Architectures and algorithms for millisecond-scale molecular dynamics simulations of proteinsDavid E. Shaw. [doi]
- Temporal instruction fetch streamingMichael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos. 1-10 [doi]
- A distributed processor state management architecture for large-window processorsIsidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco A. Ramírez, Adrián Cristal, Mateo Valero. 11-22 [doi]
- Strategies for mapping dataflow blocks to distributed hardwareBehnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley. 23-34 [doi]
- Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherenceNatalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti. 35-46 [doi]
- Token tenure: PATCHing token counting using directory-based cache coherenceArun Raghavan, Colin Blundell, Milo M. K. Martin. 47-58 [doi]
- Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRsXi E. Chen, Tor M. Aamodt. 59-70 [doi]
- Implementing high availability memory with a duplication cacheNidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan. 71-82 [doi]
- A novel cache architecture with enhanced performance and securityZhenghong Wang, Ruby B. Lee. 83-93 [doi]
- A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tagsMohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood. 94-105 [doi]
- SHARK: Architectural support for autonomic protection against stealth by rootkit exploitsVikas R. Vasisht, Hsien-Hsin S. Lee. 106-116 [doi]
- Testudo: Heavyweight security analysis via statistical samplingJoseph L. Greathouse, Ilya Wagner, David A. Ramos, Gautam Bhatnagar, Todd M. Austin, Valeria Bertacco, Seth Pettie. 117-128 [doi]
- Facelift: Hiding and slowing down aging in multicoresAbhishek Tiwari, Josep Torrellas. 129-140 [doi]
- The StageNet fabric for constructing resilient multicore systemsShantanu Gupta, Shuguang Feng, Amin Ansari, Jason A. Blome, Scott A. Mahlke. 141-151 [doi]
- From SODA to scotch: The evolution of a wireless baseband processorMark Woh, Yuan Lin, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid, Mladen Wilder, Krisztián Flautner. 152-163 [doi]
- Tradeoffs in designing accelerator architectures for visual computingAqeel Mahesri, Daniel R. Johnson, Neal C. Crago, Sanjay J. Patel. 164-175 [doi]
- Toward a multicore architecture for real-time ray-tracingVenkatraman Govindaraju, Peter Djeu, Karthikeyan Sankaralingam, Mary Vernon, William R. Mark. 176-187 [doi]
- Power to the people: Leveraging human physiological traits to control microprocessor frequencyAlex Shye, Yan Pan, Ben Scholbrock, J. Scott Miller, Gokhan Memik, Peter A. Dinda, Robert P. Dick. 188-199 [doi]
- Prefetch-Aware DRAM ControllersChang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt. 200-209 [doi]
- Mini-rank: Adaptive DRAM architecture for improving memory power efficiencyHongzhong Zheng, Jiang Lin, Zhao Zhang, Eugene Gorbatov, Howard David, Zhichun Zhu. 210-221 [doi]
- Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiencyHaiming Liu, Michael Ferdman, Jaehyuk Huh, Doug Burger. 222-233 [doi]
- Notary: Hardware techniques to enhance signaturesLuke Yen, Stark C. Draper, Mark D. Hill. 234-245 [doi]
- Dependence-aware transactional memory for increased concurrencyHany E. Ramadan, Christopher J. Rossbach, Emmett Witchel. 246-257 [doi]
- Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute bufferLivio Soares, David Tam, Michael Stumm. 258-269 [doi]
- CPR: Composable performance regression for scalable multiprocessor modelsBenjamin C. Lee, Jamison Collins, Hong Wang, David Brooks. 270-281 [doi]
- Online design bug detection: RTL analysis, flexible mechanisms, and evaluationKypros Constantinides, Onur Mutlu, Todd M. Austin. 282-293 [doi]
- Verification of chip multiprocessor memory systems using a relaxed scoreboardOfer Shacham, Megan Wachs, Alex Solomatnikov, Amin Firoozshahian, Stephen Richardson, Mark Horowitz. 294-305 [doi]
- A performance-correctness explicitly-decoupled architectureAlok Garg, Michael C. Huang. 306-317 [doi]
- Coordinated management of multiple interacting resources in chip multiprocessors: A machine learning approachRamazan Bitirgen, Engin Ipek, José F. Martínez. 318-329 [doi]
- Copy or Discard execution model for speculative parallelization on multicoresChen Tian, Min Feng, Vijay Nagarajan, Rajiv Gupta. 330-341 [doi]
- Token flow controlAmit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha. 342-353 [doi]
- Adaptive data compression for high-performance low-power on-chip networksYuho Jin, Ki Hwan Yum, Eun Jung Kim. 354-363 [doi]
- Efficient unicast and multicast support for CMPsSamuel Rodrigo, Jose Flich, José Duato, Mark Hummel. 364-375 [doi]
- Power reduction of CMP communication networks via RF-interconnectsM.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam. 376-387 [doi]
- Evaluating the effects of cache redundancy on profitAbhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary. 388-398 [doi]
- NBTI tolerant microarchitecture design in the presence of process variationXin Fu, Tao Li, José A. B. Fortes. 399-410 [doi]
- Shapeshifter: Dynamically changing pipeline width and speed to address process variationsEric Chun, Zeshan Chishti, T. N. Vijaykumar. 411-422 [doi]
- EVAL: Utilizing processors with variation-induced timing errorsSmruti R. Sarangi, Brian Greskamp, Abhishek Tiwari, Josep Torrellas. 423-434 [doi]
- Microarchitecture soft error vulnerability characterization and mitigation under 3D integration technologyWangyuan Zhang, Tao Li. 435-446 [doi]
- Low-power, high-performance analog neural branch predictionRenée St. Amant, Daniel A. Jiménez, Doug Burger. 447-458 [doi]
- Reconfigurable energy efficient near threshold cache architecturesRonald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David Blaauw, Dennis Sylvester, Krisztián Flautner. 459-470 [doi]