Table of Contents

• A minicomputerized automatic layout system for two-layer printed wiring boardsIkuo Nishioka, Takuji Kurimoto, Hisao Nishida. 1-11 [doi]
• A multi-contouring algorithmIvan Dobes. 12 [doi]
• A rectangle-probe router for multilayer P.C. boardsW. G. Cage, Robert J. Smith II. 13-22 [doi]
• Some theoretical aspects of algorithmic routingPrathima Agrawal, Melvin A. Breuer. 23-31 [doi]
• Prediction of wiring space requirements for LSIWilliam R. Heller, W. F. Michail, Wilm E. Donath. 32-42 [doi]
• Computer/interactive cleanup of non-gridded PWB's after automatic routingDonald P. Peterson. 43-57 [doi]
• A new look at test generation and verificationPredrag G. Kovijanic. 58-63 [doi]
• An automated simultaneous probing system for testing complex logic assemblies 'the bed of nails system'R. H. Somaia. 64-67 [doi]
• Computer aided test pattern generation for digital processorsKlaus Pfeuffer. 68-77 [doi]
• Automatic test generation for large digital circuitsAkihiko Yamada, Nobuo Wakatsuki, Hideo Shibano, Osamu Itoh, Kyoji Tomita, Shigehiro Funatsu. 78-83 [doi]
• Heuristic enhancement of an algorithmic test generatorR. E. Strebendt. 84-87 [doi]
• Simulator-oriented fault test generatorThomas J. Snethen. 88-93 [doi]
• Tools for map graphicsPatricia Fulton. 94-100 [doi]
• Flight test analysis of missile control systemsMark Domaszewicz. 101-108 [doi]
• MIDAS an on-line real time material systemRichard S. Hall. 109-111 [doi]
• Using a computer aided graphics system to help design and draft automotive componentsNed L. Brown. 112-117 [doi]
• Fault modeling in a hierarchical simulatorJames J. Strunge. 118-127 [doi]
• Concurrent fault simulation and functional level modelingMiron Abramovici, Melvin A. Breuer, K. Kumar. 128-137 [doi]
• Floss: An approach to automated layout for high-volume designsY. Eric Cho, A. J. Korenjak, David E. Stockton. 138-141 [doi]
• Analytical power/timing optimization technique for digital systemAlbert E. Ruehli, Peter K. Wolff Sr., Gerald Goertzel. 142-146 [doi]
• An experimental system for power/timing optimization of LSI chipsBarbara J. Agule, Jean Davies Lesser, Albert E. Ruehli, Peter K. Wolff Sr.. 147-152 [doi]
• The siemens-avesta-system for computer-aided design of MOS-standard cell circuitsKonrad W. Koller, Ulrich Lauther. 153-157 [doi]
• Automatic ECL LSI designNigel R. Crocker, R. W. McGuffin, A. Micklethwaite. 158-167 [doi]
• A production PCB layout system on a minicomputerK. Bedard, Serge Fournier, B. Shastry, U. Stockburger. 168-173 [doi]
• DOCIL: An automatic system for printed circuit board (PCB) designing. A board description language and an algorithm to connect a set of pointsTeresa de Pedro, Ricardo García. 174-181 [doi]
• A human engineered PCB design systemAndrew J. Matthews. 182-186 [doi]
• A concept for the editing of hardware resulting in an automatic hardware-editorFranz J. Rammig. 187-193 [doi]
• Simulation of large communications networks using SPINI. L. Morris, J. McNulty, R. Gee. 194-204 [doi]
• Logic design automation of diagnosable MOS combinational logic networksYacoub M. El-Ziq, Stephen Y. H. Su. 205-215 [doi]
• Practical experiences from signal probability simulation of digital designsBengt Magnhagen. 216-219 [doi]
• Detection of static and dynamic hazards in logic netsAjoy K. Bose, Stephen A. Szygenda. 220-224 [doi]
• Simulation techniques for microprocessorsJames R. Armstrong, Garry Woodruff. 225-229 [doi]
• An efficient method of fault simulation for digital circuits modeled from boolean gates and memoriesDonald M. Schuler, Roger K. Cleghorn. 230-238 [doi]
• Uncertainty and optimization in the design of building subsystemsElliott E. Dudnik. 239-243 [doi]
• Symbols, graphics and architectural education: The pagan experienceMichael Kennedy. 244-253 [doi]
• An affordable approach to an architectural computer systemDonald E. Bergeson, Robert Babbin. 254-264 [doi]
• Evolution of a spatial allocation system: AllocateBarry Jackson. 265 [doi]
• THE SITE MACHINE Computer-aided instruction in architectural educationEdward F. Smith. 266-274 [doi]
• Computer aided design in North American Schools of ArchitectureRobert Simpson Frew. 275-276 [doi]
• Computer-aided design and practice in city college school of architectureGordon A. Gebert. 277-278 [doi]
• Computer-aided architectural designEric Teicholz. 279 [doi]
• Department of architecture university of illinoisKenneth E. Tanaka, Donald E. Berseson. 280 [doi]
• Computer aided design college of architecture University of KentuckyMichael Kennedy. 281 [doi]
• A second chance at automation as a design toolRobert J. Hogan. 282 [doi]
• Yale school of architectureRobert Simpson Frew. 283 [doi]
• A class of min-cut placement algorithmsMelvin A. Breuer. 284-290 [doi]
• The chip layout problem: A placement procedure for lsiK. H. Khokhani, Arvind M. Patel. 291-297 [doi]
• The chip layout problem: An automatic wiring procedureK. A. Chen, Michael Feuer, K. H. Khokhani, Ning Nan, S. Schmidt. 298-302 [doi]
• Fast algorithms for LSI artwork analysisHenry S. Baird. 303-311 [doi]
• A comprehensive approach to a connectivity audit, or a fruitful comparison of apples and orangesR. M. Allgair, D. S. Evans. 312-321 [doi]
• A layout checking system for large scale integrated circuitsKenji Yoshida, Takashi Mitsuhashi, Yasuo Nakada, Toshiaki Chiba, Kiyoshi Ogita, Shinji Nakatsuka. 322-330 [doi]
• The open shop interactive mask design operation at harris semiconductorJustin E. Harlow III. 331-335 [doi]
• Automatic optical design with accos v programMax Amon. 336-340 [doi]
• A design automation system for printed circuit board assembliesA. Bobas, J. Valihora. 341-350 [doi]
• Computer designed multilayer hybrid substrate using thick film technologyChester W. Waldvogel. 351-353 [doi]
• Design verification of large scientific computersHoward E. Krohn. 354-361 [doi]
• A Design Verification and Logic Validation SystemWilliam A. Noon. 362-368 [doi]
• Designing with LCD: language for computer designCarlo J. Evangelisti, Gerald Goertzel, Hillel Ofek. 369-376 [doi]
• An hierarchical language for the structural description of digital systemsWilliam M. van Cleemput. 377-385 [doi]
• Cost effective layout digitizing and mask pen plotting of custom microelectronic devicesRobert P. Larsen. 386-390 [doi]
• Automating analog circuit diagrams using a list processing languageRichard C. Jaffe, Joseph P. Young. 391-395 [doi]
• CASS: Computer aided schematic systemHedayat Markus Bayegan. 396-404 [doi]
• Manipulation of design dataCarol A. Linden. 405-410 [doi]
• Measuring designer performance to verify design automation systemsDonald E. Thomas, Daniel P. Siewiorek. 411-418 [doi]
• A design automation system for telephone electronic switching systemFrank E. Swiatek. 419-424 [doi]
• SWESS - the middle system of a design automation networkDenis K. Carley. 425-430 [doi]
• SPIDER - a Computer Aided Manufacturing NetworkMichael E. Walsh. 431-436 [doi]
• PIRAMED project an integrated CAD/CAM system developmentR. W. Srch. 437-444 [doi]
• CDL - A tool for concurrent hardware and software developmentJ. Robert Heath, B. D. Carroll, Terry T. Cwik. 445-449 [doi]
• Thick film substrate (Micropackage) design utilizing interactive Computer Aided Design systemsFreddie M. Christley. 450-459 [doi]
• Introduction to an LSI test systemM. Correia, F. B. Petrini. 460-461 [doi]
• A logic design structure for LSI testabilityEdward B. Eichelberger, Thomas W. Williams. 462-468 [doi]
• Automatic checking of logic design structures For compliance with testability ground rulesHumbert C. Godoy, G. B. Franklin, Peter S. Bottorff. 469-478 [doi]
• Test generation for large logic networksPeter S. Bottorff, Richard E. France, N. H. Garges, E. J. Orosz. 479-485 [doi]
• Delay test generationE. R. Hsieh, Robert A. Rasmussen, L. J. Vidunas, W. T. Davis. 486-491 [doi]
• Delay test simulationThomas M. Storey, J. W. Barry. 492-494 [doi]
• Software engineering techniques in design automation&madash;a tutorialRobert J. Smith II. 495-507 [doi]