Akihiko Yamada - researchr alias

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Viewing Publication 1 - 25 from 25

2023

Iterative User Scheduling Method for MU-MIMO-OFDM SystemsAkihiko Yamada, Satoshi Denno, Yafei Hou. gcce 2023: 168-169 [doi]

2019

Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo KomamiyaRadomir S. Stankovic, Tsutomu Sasao, Jaakko T. Astola, Akihiko Yamada. eurocast 2020: 123-130 [doi]

2018 NEC C&C Prize CeremonyAkihiko Yamada. annals, 41(2):64-66, 2019. [doi]

Parametron and Relay Computers Exhibition Held at Tokyo University of Science in November, 2018Akihiko Yamada. annals, 41(1):61-63, 2019. [doi]

2018

IPSJ Certifies 100 IP Technology Heritage Artifacts in 10 YearsAkihiko Yamada. annals, 40(3):105-112, 2018. [doi]

2012

Events and SightingsAkihiko Yamada, Dag Spicer. annals, 34(3):70-73, 2012. [doi]

2008

Robust Face Recognition Based on Modified ICA without Training Sample of Test SubjectsXian-Hua Han, Yen-Wei Chen, Akihiko Yamada, Hideto Fujita. iih-msp 2008: 701-704 [doi]

Events and SightingsChigusa Kita, Thomas Haigh, Dag Spicer, Akihiko Yamada, Thomas J. Misa. annals, 30(2):64-67, 2008. [doi]

2007

Events and SightingsChigusa Kita, Dag Spicer, Anne Fitzpatrick, Akihiko Yamada. annals, 29(2):66-69, 2007. [doi]

2006

Multi-subregion-based probabilistic approach to pose-invariant face recognitionAkihiko Yamada, Takeo Kanade. scjapan, 37(8):68-76, 2006. [doi]

2003

Multi-subregion based probabilistic approach toward pose-invariant face recognitionTakeo Kanade, Akihiko Yamada. cira 2003: 954-959 [doi]

1998

A design method OF 2-D axial-symmetric paraunitary filter banks with a lattice structureShogo Muramatsu, Akihiko Yamada, Hitoshi Kiya. eusipco 1998: 1-4 [doi]

1996

A design method for oversampled paraunitary DFT filter banks using householder factorizationK. Kajita, Hiroyuki Kobayashi, Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya. eusipco 1996: 1-4 [doi]

1990

Challenge of design and test of ultra-large-scale circuitsAkihiko Yamada. itc 1990: 23 [doi]

1989

Scan design at NECShigehiro Funatsu, Masato Kawai, Akihiko Yamada. dt, 6(3):50-51, 1989. [doi]

Logic simulation engines in JapanShigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada. dt, 6(5):40-49, 1989. [doi]

Design Automation for Large Mainframes and Supercomputers in NECAkihiko Yamada. ifip 1989: 531

1982

Timing verification system based on delay time hierarchical natureMinoru Nomura, Shinichi Sato, Nobuo Takano, Toshinori Aoyama, Akihiko Yamada. dac 1982: 622-628 [doi]

MDS: An improved total system for firmware developmentKazutoshi Takahashi, Etsuo Takahashi, Tatsushige Bitoh, Toshinori Aoyama, Akihiko Yamada. micro 1982: 50-56 [doi]

1981

Hierarchical design verification for large digital systemsTohru Sasaki, Akihiko Yamada, Toshinori Aoyama, Katsutoshi Hasegawa, Shunichi Kato, Shinichi Sato. dac 1981: 105-112 [doi]

Design automation status in JapanAkihiko Yamada. dac 1981: 43-50 [doi]

1980

MIXS: A mixed level simulator for large digital system logic verificationTohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu. dac 1980: 626-633 [doi]

1978

Automatic System Level Test Generation and Fault Location for Large Digital SystemsAkihiko Yamada, Nobuo Wakatsuki, T. Fukui, Shigehiro Funatsu. dac 1978: 347-352 [doi]

1977

Automatic test generation for large digital circuitsAkihiko Yamada, Nobuo Wakatsuki, Hideo Shibano, Osamu Itoh, Kyoji Tomita, Shigehiro Funatsu. dac 1977: 78-83 [doi]

1974

Microprogramming Design support SystemAkihiko Yamada, Akihiro Kawaguchi, Kazutoshi Takahashi, Shunichi Kato. dac 1974: 137-142 [doi]

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